ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE

• Main Authors: TAKEUCHI YOHEI, NISHIMURA JUN, IWASE YASUAKI, TAGAWA AKIRA
• Format: Patent
• Language: English; Japanese
• Published: 02.12.2022
• Subjects: ADVERTISING; BASIC ELECTRIC ELEMENTS; CRYPTOGRAPHY; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; DISPLAY; DISPLAYING; EDUCATION; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FREQUENCY-CHANGING; LABELS OR NAME-PLATES; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; SEALS; SEMICONDUCTOR DEVICES; SIGNS; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

To provide an active matrix substrate with which it is possible to suppress a decrease in display quality.SOLUTION: An active matrix substrate includes: a first pixel region Px (b1) defined by mutually adjacent first and second source bus lines SLb, SLc and mutually adjacent first and second gate bus lines GLa, GLb; and a first pixel electrode PEb1 associated with the first pixel region and a first oxide semiconductor TFT20b1. The first oxide semiconductor TFT has an oxide semiconductor layer 7 and a gate electrode electrically connected to the first gate bus line, the oxide semiconductor layer including a channel region 7c and a resistance region that includes a first region 7s and a second region 7d respectively located at both ends of the channel region 7c, the resistance region extending to other pixel region Px (a2) across the first source line SLb when seen from the normal direction of a substrate 1 and partially overlapping other pixel electrode PEa2 arranged in the other pixel region via an insulating layer.SELECTED DRAWING: Figure 2A 【課題】表示品位の低下を抑制し得るアクティブマトリクス基板を提供する。【解決手段】アクティブマトリクス基板は、互いに隣接する第１および第２ソースバスラインＳＬｂ、ＳＬｃ、および、互いに隣接する第１および第２ゲートバスラインＧＬａ、ＧＬｂによって画定された第１画素領域Ｐｘ（ｂ１）と、第１画素領域に対応付けられた第１画素電極ＰＥｂ１および第１酸化物半導体ＴＦＴ２０ｂ１とを含み、第１酸化物半導体ＴＦＴは、酸化物半導体層７と、第１ゲートバスラインに電気的に接続されたゲート電極とを有し、酸化物半導体層は、チャネル領域７ｃと、その両側にそれぞれ位置する第１領域７ｓおよび第２領域７ｄを含む低抵抗領域とを含み、低抵抗領域は、基板１の法線方向から見たとき、第１ソースバスラインＳＬｂを横切って他の画素領域Ｐｘ（ａ２）まで延び、他の画素領域に配置された他の画素電極ＰＥａ２と絶縁層を介して部分的に重なっている。【選択図】図２Ａ