FRONT END CIRCUIT AND ENCODER
To provide a front end circuit capable of reducing influence by the offset voltage of an amplifier.SOLUTION: A front end circuit includes: a pre-stage amplifier 1 for amplifying input signals IN+ and IN-; a switching circuit 4 for alternatively inputting the input signals IN+ and IN- into the input...
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Main Authors | , , , |
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Format | Patent |
Language | English Japanese |
Published |
06.10.2022
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a front end circuit capable of reducing influence by the offset voltage of an amplifier.SOLUTION: A front end circuit includes: a pre-stage amplifier 1 for amplifying input signals IN+ and IN-; a switching circuit 4 for alternatively inputting the input signals IN+ and IN- into the input terminals 1A and 1B of the pre-stage amplifier 1; a switched capacitor circuit 2 for sampling the input signals IN+ and IN- amplified by the pre-stage amplifier 1; an integration circuit 3 for outputting a differential signal obtained by integrating two sampled signals; and a switching circuit 5 constituted to switch a connection relationship between the switched capacitor circuit 2 and the integration circuit 3. The switching circuits 4 and 5 switch connection relationships between the pre-stage amplifier 1 and the input terminals TIN+ and TIN- and a connection relationship between the switched capacitor circuit 2 and the integration circuit 3 so as to sample the input signals IN+ and IN- amplified by the pre-stage amplifier 1 with double correlation.SELECTED DRAWING: Figure 6
【課題】増幅器のオフセット電圧による影響を低減できるフロントエンド回路を提供すること。【解決手段】前段増幅器1は、入力信号IN+及びIN-を増幅する。切替回路4は、入力信号IN+及びIN-を前段増幅器1の入力端子1A及び1Bへ択一的に入力する。スイッチトキャパシタ回路2は、前段増幅器1で増幅された入力信号IN+及びIN-をサンプリングする。積分回路3は、サンプリングされた2つの信号を積分した差動信号を出力する。切替回路5は、スイッチトキャパシタ回路2と積分回路3との間の接続関係を切り替え可能に構成される。切替回路4及び5は、前段増幅器1で増幅された入力信号IN+及びIN-が二重相関サンプリングされるように、前段増幅器1と入力端子TIN+及びTIN-との間の接続関係及びスイッチトキャパシタ回路2と積分回路3との間の接続関係を切り替える。【選択図】図6 |
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Bibliography: | Application Number: JP20210050175 |