INTEGRATED CIRCUIT DEVICE AND OSCILLATOR
To provide an integrated circuit device and the like capable of suppressing reduction in heating performance caused by parasitic resistance of a heat generating transistor.SOLUTION: An integrated circuit device 20 includes a heat generating circuit 22 controlled on the basis of a temperature control...
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Main Author | |
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Format | Patent |
Language | English Japanese |
Published |
26.09.2022
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Subjects | |
Online Access | Get full text |
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Summary: | To provide an integrated circuit device and the like capable of suppressing reduction in heating performance caused by parasitic resistance of a heat generating transistor.SOLUTION: An integrated circuit device 20 includes a heat generating circuit 22 controlled on the basis of a temperature control signal. The heat generating circuit 22 includes: a heat generating transistor TR that has a plurality of parallel-connected transistors T1 to T6 whose gate voltages are controlled on the basis of the temperature control signal; a metal wire ALS overlapped with the plurality of transistors T1 to T6 in a plan view and that supplies the ground to a source of the heat generating transistor TR; and a plurality of vias VC whose one end is connected with the metal wire ALS and whose the other end is connected with a plurality of source regions of the plurality of transistors T1 to T6. The plurality of vias VC are provided at positions overlapped with the plurality of source regions in a plan view.SELECTED DRAWING: Figure 6
【課題】発熱トランジスターの寄生抵抗に起因する発熱性能の低下を抑制できる集積回路装置等の提供。【解決手段】集積回路装置20は、温度制御信号に基づいて制御される発熱回路22を含み、発熱回路22は、温度制御信号に基づいてゲート電圧が制御され且つ並列接続された複数のトランジスターT1~T6を有する発熱トランジスターTRと、複数のトランジスターT1~T6と平面視において重なり、発熱トランジスターTRのソースにグランドを供給する金属配線ALSと、一端が金属配線ALSに接続され、他端が複数のトランジスターT1~T6の複数のソース領域に接続される複数のビアVCを含む。そして複数のビアVCは、平面視において、複数のソース領域と重なる位置に設けられる。【選択図】図6 |
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Bibliography: | Application Number: JP20210038950 |