SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• Main Authors: TAKAGIWA KAZUMI, SUMIDA HITOSHI
• Format: Patent
• Language: English; Japanese
• Published: 21.09.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device capable of securing a proof pressure while suppressing increase of a chip size.SOLUTION: A semiconductor device comprises: a semiconductor layer 1 of a first conductivity type; a well region 2 of a second conductivity type, provided onto an upper part of the semiconductor layer 1; base regions 4a and 4b of the second conductivity type, provided onto the upper part of the well region 2; carrier supply regions 6a and 6b of the first conductivity type, provided onto the upper part of the base regions 4a and 4b; a drift region 3 of the first conductivity type, provided onto the top part of the well region 2 and provided so as to be separated from the base regions 4a and 4b; a carrier acceptance region 5 of the first conductivity type, provided onto the top part of the drift region 3; gate electrodes 11a and 11b provided via a gate insulator 12 onto an upper surface of the well region 2 nipped between the base regions 4a and 4b and the drift region 3; and punch-through prevention regions 9a and 9b of the second conductivity type of an impurity density, provided onto the upper part of the well region 2 and different from the base regions 4a and 4b.SELECTED DRAWING: Figure 1 【課題】チップサイズの増大を抑制しつつ、耐圧を確保することができる半導体装置を提供する。【解決手段】第１導電型の半導体層１と、半導体層１の上部に設けられた第２導電型のウェル領域２と、ウェル領域２の上部に設けられた第２導電型のベース領域４ａ，４ｂと、ベース領域４ａ，４ｂの上部に設けられた第１導電型の担体供給領域６ａ，６ｂと、ウェル領域２の上部に設けられ、ベース領域４ａ，４ｂと離間して設けられた第１導電型のドリフト領域３と、ドリフト領域３の上部に設けられた第１導電型の担体受領領域５と、ベース領域４ａ，４ｂ及びドリフト領域３の間に挟まれたウェル領域２の上面にゲート絶縁膜１２を介して設けられたゲート電極１１ａ，１１ｂと、ウェル領域２の上部に設けられ、ベース領域４ａ，４ｂと異なる不純物濃度の第２導電型のパンチスルー防止領域９ａ，９ｂを備える。【選択図】図１