LAMINATED SEMICONDUCTOR DEVICE

• Main Author: MOTOYOSHI MAKOTO
• Format: Patent
• Language: English; Japanese
• Published: 17.05.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a laminated semiconductor device capable of being hermetically sealed even when using a semiconductor chip in which a pitch interval between an input electrode and an output electrode is made fine.SOLUTION: A laminated semiconductor device includes an upper semiconductor substrate 11B, an upper insulation layer 13B that is over a main surface of the upper semiconductor substrate 11B, an upper sealing pattern portion that encloses sides of the upper insulation layer 13B, a lower chip 10A that is arranged so that a chip mounting region composed of at least a portion of the main surface faces the upper insulation layer 13B, an upper sealing pattern portion (14B, 15o, 15i) that is arranged on a main surface of the lower chip 10A, constitutes a pattern corresponding to the arrangement of the upper sealing pattern portion, encloses sides of the chip mounting region, and forms a metallurgical connection body (14A, 15o, 15i) by solid phase diffusion bonding with the upper sealing pattern portion. In each of the chip mounting region, the upper insulation layer 13B, and metallurgical connection body, an air tight space is formed.SELECTED DRAWING: Figure 6 【課題】入出力電極のピッチ間隔が微細化された半導体チップが用いられる場合であっても、気密封止が可能な積層型半導体装置を提供する。【解決手段】上側半導体基板１１Ｂと、上側半導体基板１１Ｂの主面上の上側絶縁層１３Ｂと、上側絶縁層１３Ｂの周辺に沿って周回する上側封止パターン部と、上側絶縁層１３Ｂに、主面の少なく共一部で構成されるチップ搭載領域が対向するように配置された下側チップ１０Ａと、下側チップ１０Ａの主面上に配置され、上側封止パターン部の配置に対応したパターンを構成し、チップ搭載領域の周辺を周回し、上側封止パターン部との固相拡散接合により金属学的接続体（１４Ａ，１５o，１５i）を構成する上側封止パターン部（１４Ｂ，１５o，１５i）を備える。チップ搭載領域、上側絶縁層１３Ｂ及び金属学的接続体の内部に気密空間を形成している。【選択図】図６