METHOD FOR EVALUATING SiC SUBSTRATE, METHOD FOR PRODUCING SiC EPITAXIAL WAFER, AND METHOD FOR PRODUCING SiC DEVICE

• Main Author: ARAKI TAKUMA
• Format: Patent
• Language: English; Japanese
• Published: 02.05.2022
• Subjects: AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUSPOLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR; BASIC ELECTRIC ELEMENTS; CHEMISTRY; CRYSTAL GROWTH; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; METALLURGY; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE; REFINING BY ZONE-MELTING OF MATERIAL; SEMICONDUCTOR DEVICES; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE; SINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL ORUNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL

To provide a method for evaluating an SiC substrate that can identify penetration failures at low cost and with efficiency.SOLUTION: A method for evaluating an SiC substrate includes: an image acquisition step for acquiring photoluminescent images of two or more SiC substrates cut from an ingot grown from the same seed crystal; an extraction step for extracting the position of a failure in each of the two or more SiC substrates; and a determination step for determining whether the failure is a penetration failure by comparison of the position of the failure and an S/N ratio. The determination step includes a first determination stage for determining whether the failure of a wafer for comparison is within a predetermined range relative to a failure of a wafer for reference, and a second determination step for determining whether the S/N ratio of the failure of the wafer for comparison, which has been determined to be within the predetermined range in the first determination stage, is lower than or equal to the S/N ratio of the wafer for reference.SELECTED DRAWING: Figure 1 【課題】貫通欠陥を低コストかつ効率的に識別できるＳｉＣ基板の評価方法を提供することを目的とする。【解決手段】本実施形態にかかるＳｉＣ基板の評価方法は、同一の種結晶から成長したインゴットから切り出された２以上のＳｉＣ基板のフォトルミネッセンス像を取得する画像取得工程と、前記２以上のＳｉＣ基板のそれぞれにおける欠陥の位置を抽出する抽出工程と、欠陥の位置及びＳ／Ｎ比を比較し、前記欠陥が貫通欠陥であるか否かを判定する判定工程と、を有し、前記判定工程は、比較する比較ウェハの欠陥が基準ウェハにおける欠陥に対して所定の範囲内にあるかを判定する第１判定工程と、前記第１判定工程で、前記所定の範囲内にあると判定された前記比較ウェハの欠陥のＳ／Ｎ比が前記基準ウェハのＳ／Ｎ比以下であるかを判定する第２判定工程と、を有する。【選択図】図１