SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD FOR THE SAME

To provide a semiconductor storage device capable of accumulating more charges.SOLUTION: A semiconductor storage device according to an embodiment includes a semiconductor substrate, a first insulating layer, a second insulating layer having the first insulating layer between the second insulating l...

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Bibliographic Details
Main Authors IKENO DAISUKE, KAJITA AKIHIRO
Format Patent
LanguageEnglish
Japanese
Published 30.03.2022
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Summary:To provide a semiconductor storage device capable of accumulating more charges.SOLUTION: A semiconductor storage device according to an embodiment includes a semiconductor substrate, a first insulating layer, a second insulating layer having the first insulating layer between the second insulating layer and the semiconductor substrate, a semiconductor layer being provided between the first insulating layer and the second insulating layer and extending in a first direction parallel to a surface of the semiconductor substrate, a gate electrode layer extending in a direction perpendicular to the surface, a first insulating film provided between the semiconductor layer and the gate electrode layer, a second insulating film provided between the first insulating film and the gate electrode layer, between the first insulating layer and the gate electrode layer, and between the second insulating layer and the gate electrode layer and disposed in contact with the first insulating layer and the second insulating layer, a polycrystalline silicon region provided between the first insulating film and the second insulating film, and a metal film being provided between the polycrystalline silicon region and the second insulating film and containing titanium (Ti) and silicon (Si).SELECTED DRAWING: Figure 1 【課題】電荷蓄積量を増加させることが可能な半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置は、半導体基板と、第1の絶縁層と、半導体基板との間に第1の絶縁層を挟む第2の絶縁層と、第1の絶縁層と第2の絶縁層との間に設けられ、半導体基板の表面に平行な第1の方向に延びる半導体層と、表面に垂直な方向に延びるゲート電極層と、半導体層とゲート電極層との間に設けられた第1の絶縁膜と、第1の絶縁膜とゲート電極層との間、第1の絶縁層とゲート電極層との間、及び、第2の絶縁層とゲート電極層との間に設けられ、第1の絶縁層及び第2の絶縁層と接する第2の絶縁膜と、第1の絶縁膜と第2の絶縁膜との間に設けられた多結晶シリコン領域と、多結晶シリコン領域と第2の絶縁膜との間に設けられ、チタン(Ti)及びシリコン(Si)を含む金属膜と、を備える。【選択図】図1
Bibliography:Application Number: JP20200156745