SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

• Main Author: HOSHI YASUYUKI
• Format: Patent
• Language: English; Japanese
• Published: 18.03.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device with high reliability that can be manufactured (produced) easily, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor substrate 10 is manufactured by stacking only first and second n-type epitaxial layers 72 and 73 on an n+ type start substrate 71. A front surface of the semiconductor substrate 10 is a flat surface continuing from an active region 1 to a chip end part. In an edge terminal region 2, an annular FLR 20 having a plurality of p-type FLR regions 24 disposed apart from each other concentrically surrounding the periphery of the active region 1 is provided as a breakdown voltage structure. Each of the plurality of p-type FLR regions 24 includes a laminate structure formed by a plurality of p-type regions (partial FLRs) adjacent in a depth direction Z and formed by ion injection of p-type impurities every time the first and second n-type epitaxial layers 72 and 73 composing the semiconductor substrate 10 are epitaxially grown. By adjusting the impurity concentration and the number of laminations of the partial FLR in the p-type FLR region 24, a predetermined withstanding voltage can be obtained.SELECTED DRAWING: Figure 2 【課題】作製（製造）が簡易であり、信頼性の高い半導体装置および半導体装置の製造方法を提供すること。【解決手段】半導体基板１０はｎ+型出発基板７１上に第１，２ｎ-型エピタキシャル層７２，７３のみを積層して作製されており、半導体基板１０のおもて面は活性領域１からチップ端部まで連続する平坦面である。エッジ終端領域２に、耐圧構造として、活性領域１の周囲を同心状に囲む複数のｐ型ＦＬＲ領域２４を互いに離して配置した環状のＦＬＲ２０が設けられている。複数のｐ型ＦＬＲ領域２４は、それぞれ、半導体基板１０を構成する第１，２ｎ-型エピタキシャル層７２，７３をエピタキシャル成長させるごとにｐ型不純物のイオン注入を行って形成され深さ方向Ｚに隣接する複数のｐ型領域（部分ＦＬＲ）で構成された積層構造を有する。ｐ型ＦＬＲ領域２４の部分ＦＬＲの積層数や不純物濃度を調整することで、所定耐圧が得られる。【選択図】図２