SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

To provide a semiconductor device that avoids presence of some sharp corner part between an upper dielectric layer and a lower dielectric layer, and effectively reduces problems related to a too small thickness of the upper dielectric layer at a bottom part thereof to prevent a current from leaking....

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Bibliographic Details
Main Authors MAOJIE CONG, SONG JINXING, YUAN JIAGUI
Format Patent
LanguageEnglish
Japanese
Published 18.02.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:To provide a semiconductor device that avoids presence of some sharp corner part between an upper dielectric layer and a lower dielectric layer, and effectively reduces problems related to a too small thickness of the upper dielectric layer at a bottom part thereof to prevent a current from leaking.SOLUTION: A semiconductor device has a shield gate trench electric field effect transistor (FET) formed in a cell region 100A, and also has a super-barrier rectifier (SBR) formed in a non-cell region (source connection region 100B). The second dielectric layer 200B of the SBR has an upper dielectric layer 220B and a lower dielectric layer 210B, and those are smoothly connected at a peaked part which is gradually reduced in a thickness.SELECTED DRAWING: Figure 3 【課題】上部誘電体層と、下部誘電体層との間に何らかの鋭い角部が存在することを回避し、その底部における上部誘電体層の過度に小さな厚さの問題を効果的に緩和し、電流リークを防止する半導体装置を提供する。【解決手段】半導体装置において、セル領域１００Ａにシールドゲートトレンチ電界効果トランジスタ（ＦＥＴ）が形成され、非セル領域（ソース接続領域１００Ｂ）にスーパーバリア整流器（ＳＢＲ）が形成される。ＳＢＲは、第２の誘電体層２００Ｂが上部誘電体層２２０Ｂと下部誘電体層２１０Ｂとを有し、これらは、徐々に厚さを薄くしたビーク状部分によって滑らかに接続されている。【選択図】図３
Bibliography:Application Number: JP20210018701