STORAGE DEVICE INCLUDING CIRCUITS FOR INSTRUCTION ACQUISITION, DECODING, EXECUTION, LOGICAL ADDRESS, AND BUS NET CIRCUIT

• Main Author: YOKOYAMA KATSUNORI
• Format: Patent
• Language: English; Japanese
• Published: 16.02.2022
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

To solve the problem of portable apparatuses that although five stages of instruction acquisition, decoding, address generation, operand acquisition and execution are performed on the CPU side and a memory unit is specialized in storage function, the CPU and apparatus capacities have reached limits due to advances in applications, which has brought about burdens of repeated development and consumption and environment problems, calling for means for persistently augmenting apparatus capacities.SOLUTION: A storage device at least includes a first and a second memory array, a first access path for selecting by an address signal, the first memory array including a second access path for selecting from multi-access cell and data signal, assuming the roles of instruction acquisition and operand acquisition. In the middle between a memory bus and the memory unit, a circuit for instruction decoding and execution and a circuit for relaying of intersections of data and address signals and physical and logical address generation are provided. Segments are constituted including a bus circuit and dynamically expanded to the bus net, memory function and five stage functions of the CPU are dynamically augmented to the address space, and memory increasing means contributes to sustainable capacity enhancements.SELECTED DRAWING: Figure 1 【課題】携帯機器では、命令取得、解読、アドレス生成、オペランド取得、及び実行の５段階はＣＰＵ側で行い、メモリ部は、記憶機能に特化していた。しかし、アプリが高度化し、ＣＰＵと機器の能力が限界に至り、開発と消費を繰り返す負担問題や環境問題を招き、機器の能力を持続的に増強する手段が課題であった。【解決手段】少なくとも、第１と第２のメモリ配列を有し、アドレス信号で選択する第１のアクセス経路と、第１のメモリ配列は、マルチアクセスのセルとデータ信号から選択する第２のアクセス経路を有して命令取得、ペランド取得を担い、メモリバスからメモリ部との中間に、命令解読、実行の回路と、データやアドレス系信号の交差の中継、物理と論理のアドレス生成の回路を設け、Ｂｕｓ回路を含んでセグメントを構成し、バスネット上に動的に展開し、メモリ機能とＣＰＵの５段階機能をアドレス空間上に動的に増殖し、メモリ増量の手段で持続的な能力の増強に寄与する。【選択図】図１