DISPLAY DEVICE

• Main Authors: LEE SANG-GUL, RYU WON SANG, SHIN SUNG SOO
• Format: Patent
• Language: English; Japanese
• Published: 18.01.2022
• Subjects: ADVERTISING; BASIC ELECTRIC ELEMENTS; CRYPTOGRAPHY; DISPLAY; DISPLAYING; EDUCATION; ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; LABELS OR NAME-PLATES; PHYSICS; SEALS; SEMICONDUCTOR DEVICES; SIGNS

To provide a display device with improved performance by arranging thin film transistors with different characteristics together on an array substrate.SOLUTION: A display device is disclosed herein. The display device includes a substrate including a display region and a non-display region. The non-display region may include a first thin film transistor and the display region may include a second thin film transistor and a third thin film transistor. The second thin film transistor includes a second semiconductor pattern and a third semiconductor pattern including a first oxide semiconductor, a second gate electrode overlapping with the second semiconductor pattern, a third gate electrode overlapping with the third semiconductor pattern, and a second source electrode and a second drain electrode where the second semiconductor pattern and the third semiconductor pattern are connected in a contact hole. The third thin film transistor includes a fourth semiconductor pattern including the first oxide semiconductor, a fourth gate electrode overlapping with the fourth semiconductor pattern, and a third source electrode and a third drain electrode connected to the fourth semiconductor pattern.SELECTED DRAWING: Figure 1 【課題】アレイ基板上に互いに異なる特性を有する薄膜トランジスタを一緒に配置して表示装置の性能を向上させる表示装置を提供する。【解決手段】本明細書は表示装置を開示する。前記表示装置は表示領域及び非表示領域を含む基板であり、非表示領域に存在する第１薄膜トランジスタと、表示領域に存在する第２薄膜トランジスタ及び第３薄膜トランジスタとを含むことができる。第２薄膜トランジスタは、第１酸化物半導体を含む第２半導体パターン及び第３半導体パターン、第２半導体パターンと重畳する第２ゲート電極、第３半導体パターンと重畳する第３ゲート電極、及び第２半導体パターンと第３半導体パターンがコンタクトホールで連結される第２ソース電極及び第２ドレイン電極を含むことができる。第３薄膜トランジスタは、第１酸化物半導体を含む第４半導体パターン、第４半導体パターンと重畳する第４ゲート電極、及び第４半導体パターンに連結される第３ソース電極及び第３ドレイン電極を含むことができる。【選択図】 図１