SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• Main Authors: SEKIGUCHI YUJI, HAYASHI YASUNOBU, YAMAZAKI TADAYUKI
• Format: Patent
• Language: English; Japanese
• Published: 13.12.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device capable of repeatedly writing and deleting data into and from a memory structure in a configuration in which the memory structure is adjacently arranged on a lateral side of a planar gate structure, and a method for manufacturing the same.SOLUTION: A semiconductor device 1 includes: a well region 21 formed in a surface part of a first principal surface 3 of a semiconductor layer 2; a source region 22 formed in a surface part of the well region 21; a drain region 23 formed in the surface part of the well region 21 at intervals from the source region 22 and partitioning a channel region 24 between itself and the source region 22; a planar gate structure 30 formed on the first principal surface 3 of the semiconductor layer 2 so as to face the channel region 24; and a memory structure 40 adjacently arranged on a lateral side of the planar gate structure 30. The memory structure 40 includes an insulation film 41 formed on the channel region 24, and a charge storage film 42 facing the channel region 24 across the insulation film 41.SELECTED DRAWING: Figure 4 【課題】プレーナゲート構造の側方にメモリ構造が隣接配置される構成において、メモリ構造がメモリ構造に対するデータの書き込みおよび消去を繰り返し行うことができる半導体装置およびその製造方法を提供する。【解決手段】半導体装置１は、半導体層２の第１主面３の表面部に形成されたウェル領域２１と、ウェル領域２１の表面部に形成されたソース領域２２と、ソース領域２２から間隔を空けてウェル領域２１の表面部に形成され、ソース領域２２との間にチャネル領域２４を区画するドレイン領域２３と、チャネル領域２４に対向するように半導体層２の第１主面３上に形成されたプレーナゲート構造３０と、プレーナゲート構造３０の側方に隣接配置されたメモリ構造４０とを含む。メモリ構造４０は、チャネル領域２４上に形成された絶縁膜４１と、絶縁膜４１を挟んでチャネル領域２４に対向する電荷蓄積膜４２とを含む。【選択図】図４