DEVICE, ARTICLE WITH DEVICE, AND MANUFACTURING METHOD

• Main Authors: OBATA KOJI, NAKA JUNICHI, NAGASAKI SUMIHISA, ARAI HIDEYUKI, HIGUCHI YUICHI
• Format: Patent
• Language: English; Japanese
• Published: 07.10.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; HANDLING RECORD CARRIERS; PHYSICS; PRESENTATION OF DATA; RECOGNITION OF DATA; RECORD CARRIERS

To provide a device, an article with the device, and a manufacturing method that can reduce possibility of breakage of a chip.SOLUTION: A device 1 comprises a base layer 2, a chip 4, and a wiring part 3. The base layer 2 is formed on a predetermined surface 50 of an article 5, and has a housing recessed part 21 on an arrangement surface 20 being an opposite side to the predetermined surface 50. The chip 4 has a first surface 41 and a second surface 42 in a thickness direction, and is arranged on a bottom surface 210 by directing the second surface 42 to the bottom surface 210 of the housing recessed part 21 of the base layer 2. The wiring part 3 has a specific portion 33 arranged on the arrangement surface 20, and is electrically connected to the chip 4. A distance H1 from the bottom surface 210 of the housing recessed part 21 to the first surface 41 of the chip 4 is less than or equal to a depth D of the housing recessed part 21.SELECTED DRAWING: Figure 3 【課題】課題は、チップの破損の可能性を低減できる、デバイス、デバイス付き物品、及び、製造方法を提供することである。【解決手段】デバイス１は、下地層２と、チップ４と、配線部３と、を備える。下地層２は、物品５の所定面５０に形成され、所定面５０とは反対側の配置面２０に収容凹部２１を有する。チップ４は、厚み方向の第１面４１及び第２面４２を有し、第２面４２を下地層２の収容凹部２１の底面２１０に向けて底面２１０に配置される。配線部３は、配置面２０に配置される特定部位３３を有し、チップ４に電気的に接続される。収容凹部２１の底面２１０からチップ４の第１面４１までの距離Ｈ１は、収容凹部２１の深さＤ以下である。【選択図】図３