STRUCTURE AND MANUFACTURING METHOD THEREOF

• Main Authors: HIGUCHI KAZUTO, OBATA SUSUMU, SHIMOKAWA KAZUO, SANO MITSUO
• Format: Patent
• Language: English; Japanese
• Published: 27.09.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To suppress the progress of etching in an in-plane direction.SOLUTION: A structure according to an embodiment includes a conductive substrate CS including semiconductor materials, one main surface S1 of the conductive substrate CS includes a first region A1 and a second region A2 adjacent to the first region A1 and having a lower height than the first region A1. The first region A1 is provided with one or more recesses TR whose bottom position is lower than that of the second region A2, and the surface region of the conductive substrate CS on the main surface S1 side includes a porous structure at a position between the one or more recesses TR and the second region A2.SELECTED DRAWING: Figure 3 【課題】面内方向へのエッチングの進行を抑制可能とする。【解決手段】実施形態の構造体は、半導体材料を含んだ導電基板ＣＳを備え、前記導電基板ＣＳの一主面Ｓ１は、第１領域Ａ１と、前記第１領域Ａ１に隣接し、前記第１領域Ａ１と比較して高さがより低い第２領域Ａ２とを含み、前記第１領域Ａ１には、底部の位置が前記第２領域Ａ２と比較してより低い１以上の凹部ＴＲが設けられ、前記導電基板ＣＳのうち前記主面Ｓ１側の表面領域は、前記１以上の凹部ＴＲと前記第２領域Ａ２との間の位置に多孔質構造を含む。【選択図】図３