SEMICONDUCTOR MODULE

• Main Authors: KATO RYOICHI, IKEDA YOSHINARI, MURATA YUMA, NAKAGOME AKITO, KANAI NAOYUKI
• Format: Patent
• Language: English; Japanese
• Published: 16.09.2021
• Subjects: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS; BASIC ELECTRIC ELEMENTS; CONTROL OR REGULATION THEREOF; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERATION; SEMICONDUCTOR DEVICES

To reduce the inductance and suppress the variation in inductance between a gate and a source.SOLUTION: A semiconductor module (1) includes an insulating substrate (2) having a main wiring layer formed on an upper surface, a positive electrode terminal (17) and a negative electrode terminal (18) arranged adjacent to each other in a line, a plurality of semiconductor elements (3a-3d) each having a gate electrode (30) and a source electrode on an upper surface, forming a first column and a second column connected electrically in parallel to each other in parallel to an arrangement direction of the positive electrode terminal and the negative electrode terminal, and disposed on the main wiring layer so that the gate electrode in the first column and the gate electrode in the second column face each other in a direction intersecting with the arrangement direction, a control wiring board (5) disposed between the first column and the second column and including a gate wiring layer (51) and a source wiring layer (50) extending in parallel to the arrangement direction, a gate wiring member (G2) connecting the gate electrode and the gate wiring layer, and a source wiring member (S2) connecting the source electrode and the source wiring layer.SELECTED DRAWING: Figure 1 【課題】ゲート・ソース間のインダクタンスの低減及びインダクタンスのバラツキの抑制をすること。【解決手段】半導体モジュール（１）は、上面に主配線層が形成された絶縁基板（２）と、隣接して一列に配列された正極端子（１７）及び負極端子（１８）と、上面にゲート電極（３０）とソース電極を有し、正極端子と負極端子の配列方向と平行して電気的に並列接続された第１列と第２列を形成し、第１列のゲート電極と第２列のゲート電極とが配列方向に交差する方向で対向するように、主配線層上に配置された複数の半導体素子（３ａ−３ｄ）と、第１列と第２列の間に配置され、配列方向と平行して延伸したゲート配線層（５１）及びソース配線層（５０）を有する制御配線基板（５）と、ゲート電極とゲート配線層とを接続するゲート配線部材（Ｇ２）と、ソース電極とソース配線層とを接続するソース配線部材（Ｓ２）と、を備える。【選択図】図１