NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
To provide a nonvolatile semiconductor memory device capable of preventing a short-circuit between adjacent wiring and reducing wiring resistance.SOLUTION: A nonvolatile semiconductor memory device according to an embodiment comprises: a first wiring layer extending in a first direction; a second wi...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
13.09.2021
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a nonvolatile semiconductor memory device capable of preventing a short-circuit between adjacent wiring and reducing wiring resistance.SOLUTION: A nonvolatile semiconductor memory device according to an embodiment comprises: a first wiring layer extending in a first direction; a second wiring layer extending in a second direction; a third wiring layer extending in the second direction and provided above in a third direction; a first memory cell arranged between the second wiring layer and the first wiring layer and including a first resistance change film; a fourth wiring layer extending in the first direction and provided above in the third direction; and a second memory cell arranged between the fourth wiring layer and the third wiring layer and including a second resistance change film. The second wiring layer includes a first surface S1 on an upper side in contact with the third wiring layer and a second surface S2 including a portion longer than the first surface in the first direction, provided separated from the first surface in the third direction, extending in the first direction, and connected to the portion longer than the first surface among the surfaces of the second wiring layer. The third wiring layer includes a third surface S3 in contact with the first surface of the second wiring layer, and the third surface is longer than the first surface in the first direction.SELECTED DRAWING: Figure 8B
【課題】隣接配線間の短絡を防止し、かつ配線抵抗を低減する。【解決手段】実施の形態に係る不揮発性半導体記憶装置は、第1方向に延伸する第1配線層と、第2方向に延伸する第2配線層と、第2方向に延伸し、第3方向上方に設けられる第3配線層と、第2配線層と第1配線層との間に配置され第1抵抗変化膜を有する第1メモリセルと、第1方向に延伸し、第3方向上方に設けられる第4配線層と、第4配線層と第3配線層との間に配置され第2抵抗変化膜を有する第2メモリセルを備える。第2配線層は、その表面のうち、第3配線層に接している上側の第1面S1及び、第1方向において第1面より長い部分を有し、第1面に対して第3方向に離れて設けられかつ、第1方向に延伸して、長い部分に接続する第2面S2を有する。第3配線層は、第3配線層の表面のうち、第2配線層の第1面に接する第3面S3を有し、第3面は第1方向において第1面より長い。【選択図】図8B |
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Bibliography: | Application Number: JP20200030578 |