WAFER CONVEYANCE UNIT AND WAFER CONVEYANCE METHOD

• Main Authors: SHIMASE AKIRA, IKESU MASATAKA, ISHIZUKA TOSHIMICHI
• Format: Patent
• Language: English; Japanese
• Published: 10.08.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To properly hold a wafer during conveyance without interfering with each function of a semiconductor failure analysis device.SOLUTION: A failure analysis unit 10 is a wafer conveyance unit that conveys a wafer W while holding the wafer in a semiconductor failure analysis device, and includes: a moun...