SEMICONDUCTOR DEVICE

• Main Authors: YAMAZAKI SHUNPEI, KUWABARA HIDEAKI, SASAKI TOSHINARI, NODA KOSEI, OHARA HIROKI
• Format: Patent
• Language: English; Japanese
• Published: 26.07.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device having a structure that is able to sufficiently reduce parasitic capacitance between wires.SOLUTION: In a thin film transistor of a bottom gate structure, an oxide insulating layer serving as a channel protective layer is formed on a part of an oxide semiconductor layer overlapping a gate electrode layer, and an oxide insulating layer covering a peripheral portion (including a side surface) of the oxide semiconductor layer is formed during the formation of the oxide insulating layer. The oxide insulating layer covering the peripheral portion (including the side surface) of the oxide semiconductor layer increases a distance from the gate electrode layer or a wiring layer (such as a source wiring layer or a capacity wiring layer) formed above or around the gate electrode layer, thereby reducing parasitic capacitance. Since the oxide insulating layer covering the peripheral portion of the oxide semiconductor layer is formed in the same step as the channel protective layer, the parasitic capacitance can be reduced without increasing the number of steps.SELECTED DRAWING: Figure 1 【課題】配線間の寄生容量を十分に低減できる構成を備えた半導体装置を提供することを課題の一とする。【解決手段】ボトムゲート構造の薄膜トランジスタにおいて、ゲート電極層と重なる酸化物半導体層の一部にチャネル保護層となる酸化物絶縁層を形成し、その酸化物絶縁層の形成時に酸化物半導体層の周縁部（側面を含む）を覆う酸化物絶縁層を形成する。酸化物半導体層の周縁部（側面を含む）を覆う酸化物絶縁層は、ゲート電極層と、その上方または周辺に形成される配線層（ソース配線層や容量配線層など）との距離を大きくし、寄生容量の低減を図る。酸化物半導体層の周縁部を覆う酸化物絶縁層は、チャネル保護層と同一工程で形成されるため、工程数の増加なく、寄生容量を低減できる。【選択図】図１