WAFER POLISHING METHOD AND SILICON WAFER

• Main Authors: KOSASA KAZUAKI, SUGIMORI KATSUHISA, NISHIOKA KAZUKI, MORITA TAKASHI
• Format: Patent
• Language: English; Japanese
• Published: 27.05.2021
• Subjects: BASIC ELECTRIC ELEMENTS; DRESSING OR CONDITIONING OF ABRADING SURFACES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS; GRINDING; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; PERFORMING OPERATIONS; POLISHING; SEMICONDUCTOR DEVICES; TRANSPORTING

To provide a wafer polishing method capable of improving nanotopographic characteristics in a site having a 2 mm square or an equivalent small area on the surface of the wafer, and a silicon wafer polished by the polishing method.SOLUTION: In a method of chemically mechanically polishing the surface of a wafer by two or more polishing steps with different polishing rates, the in-plane thickness variation (standard deviation) of a polishing pad 150 used in the polishing step with a removal allowance of 0.3 μm or more is 2.0 μm or less.SELECTED DRAWING: Figure 1 【課題】ウェーハの表面の２ｍｍスクエア又はこれと同等の小さな面積を有するサイト内のナノトポグラフィ特性を改善することが可能なウェーハの研磨方法及び当該研磨方法によって研磨されたシリコンウェーハを提供する。【解決手段】研磨レートが異なる２段以上の研磨ステップによりウェーハの表面を化学的機械研磨する方法であって、取り代が０．３μｍ以上の研磨ステップで使用する研磨パッド１５０の面内の厚みばらつき（標準偏差）が２．０μｍ以下である。【選択図】図１