VERTICAL MEMORY DEVICE
To provide a vertical memory device with improved electric characteristics.SOLUTION: A vertical memory device may include gate electrodes stacked stepwise apart from each other on a substrate along a first direction perpendicular to an upper surface of the substrate, a channel penetrating the gate e...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
30.04.2021
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a vertical memory device with improved electric characteristics.SOLUTION: A vertical memory device may include gate electrodes stacked stepwise apart from each other on a substrate along a first direction perpendicular to an upper surface of the substrate, a channel penetrating the gate electrodes and extending in the first direction, a first contact plug penetrating a pad of a first gate electrode corresponding to one of the gate electrodes, being in contact with an upper surface thereof, and penetrating at least a part of a second gate electrode formed right below the first gate electrode, a first spacer formed between the first contact plug and the opposite side wall of the first and second gate electrodes and insulating between the first contact plug and the second gate electrode, and a first embedded pattern containing an insulating material in contact with a bottom surface of the first contact plug and the first spacer.SELECTED DRAWING: Figure 46
【課題】 改善された電気的特性を有する垂直型メモリ装置を提供する。【解決手段】 垂直型メモリ装置は、基板の上面に垂直な第1方向に沿って前記基板上に互いに離隔して階段形状に積層されたゲート電極、前記ゲート電極を貫通して前記第1方向に延びたチャネル、前記ゲート電極のうちの1つである第1ゲート電極のパッドを貫通し、その上面に接触し、前記第1ゲート電極の真下層に形成された第2ゲート電極の少なくとも一部を貫通する第1コンタクトプラグ、前記第1コンタクトプラグとこれに対向する前記第1及び第2ゲート電極の側壁の間に形成されて前記第1コンタクトプラグと前記第2ゲート電極を絶縁させる第1スペーサー、及び前記第1コンタクトプラグ及び前記第1スペーサーの底面に接触し、絶縁物質を含む第1埋込パターンを備えることができる。【選択図】 図46 |
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Bibliography: | Application Number: JP20200112565 |