SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR
To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device includes: a silicon carbide layer located between a first electrode and a second electrode and having a first surface and a second surface opposite to the first surface, the silicon carbide layer inc...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English Japanese |
Published |
22.02.2021
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device includes: a silicon carbide layer located between a first electrode and a second electrode and having a first surface and a second surface opposite to the first surface, the silicon carbide layer including a trench located in a side of the first surface and having a first portion and a second portion closer to the first portion, a width of the second surface being smaller than that of the first portion, an n type first silicon carbide region, a p type second silicon carbide region between the first silicon carbide region and the first surface, a p type third silicon carbide region located between the second silicon carbide region and the first surface and having a p type impurity concentration lower than that of the second silicon carbide region, an n type fourth silicon carbide region between the third silicon carbide region and the first surface, and an n type fifth silicon carbide region located between the second portion and the second silicon carbide region and having an n type impurity concentration higher than that of the first silicon carbide region; and a gate electrode located in the trench.SELECTED DRAWING: Figure 1
【課題】オン抵抗の低減が可能な半導体装置を提供する。【解決手段】実施形態の半導体装置は、第1の電極と第2の電極との間に位置し、第1の面と、第1の面に対向する第2の面と、を有する炭化珪素層であって、第1の面の側に位置し、第1の部分と、第1の部分よりも第2の面に近く第1の部分よりも幅が小さい第2の部分と、を有するトレンチと、n型の第1の炭化珪素領域と、第1の炭化珪素領域と第1の面との間のp型の第2の炭化珪素領域と、第2の炭化珪素領域と第1の面との間に位置し、第2の炭化珪素領域よりもp型不純物濃度が低いp型の第3の炭化珪素領域と、第3の炭化珪素領域と第1の面との間のn型の第4の炭化珪素領域と、第2の部分と第2の炭化珪素領域との間に位置し、第1の炭化珪素領域よりもn型不純物濃度の高いn型の第5の炭化珪素領域と、を有する炭化珪素層と、トレンチの中に位置するゲート電極と、を備える。【選択図】図1 |
---|---|
Bibliography: | Application Number: JP20190145597 |