COMPOUND SEMICONDUCTOR HETERO JUNCTION BI-POLAR TRANSISTOR

To provide a structure of an emitter layer and a base layer, capable of suppressing an influence on a characteristic as a power amplifier of conduction band energy barrier generated at an interface of the emitter layer and the base layer in a GaAsHBT using a pseudo-lattice matching growth InGaAs in...

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Bibliographic Details
Main Author TAKATANI SHINICHIRO
Format Patent
LanguageEnglish
Japanese
Published 15.02.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:To provide a structure of an emitter layer and a base layer, capable of suppressing an influence on a characteristic as a power amplifier of conduction band energy barrier generated at an interface of the emitter layer and the base layer in a GaAsHBT using a pseudo-lattice matching growth InGaAs in the base layer.SOLUTION: In a first invention, an InGaP with CuPt type discipline is used in an emitter layer. In a second invention, a p-type impurity concentration in a portion on the emitter layer side of a pseudo-lattice matching growth InGaAs base layer is provided to be lower than that on the collector layer side.SELECTED DRAWING: Figure 1 【課題】擬似格子整合成長ＩｎＧａＡｓをベース層に用いるＧａＡｓＨＢＴにおいてエミッタ層とベース層との界面に生じる伝導帯エネルギー障壁の電力増幅器としての特性への影響を低減するエミッタ層およびベース層の構造を提供する。【解決手段】第１の発明においては、エミッタ層にＣｕＰｔ型秩序を有するＩｎＧａＰを用いる。第２の発明においては、擬似格子整合成長ＩｎＧａＡｓベース層のエミッタ層側の部分におけるｐ型不純物濃度をコレクタ層側に比べ低くする。【選択図】図１
Bibliography:Application Number: JP20190133841