SEMICONDUCTOR MODULE
To provide a semiconductor module capable of effectively suppressing a generated surge voltage.SOLUTION: A semiconductor module 100 includes: a circuit board 120 having a P-side conductive region 122 to be a positive electrode, an N-side conductive region 121 to be a negative electrode, and an O-con...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
14.01.2021
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a semiconductor module capable of effectively suppressing a generated surge voltage.SOLUTION: A semiconductor module 100 includes: a circuit board 120 having a P-side conductive region 122 to be a positive electrode, an N-side conductive region 121 to be a negative electrode, and an O-conductive region 123 to be an output, on one side surface 120a; a first semiconductor chip 60 mounted in the O-conductive region 123; a second semiconductor chip 70 mounted in the P-side conductive region 122; a cover 130 having a case 20 surrounding the circuit board 120 on which the first semiconductor chip 60 and the second semiconductor chip 70 are mounted, and an opening 131; and a snubber circuit module 200 inserted in the opening 131. The snubber circuit module 200 is connected to at least two of the P-side conductive region 122, the N-side conductive region 121 and the O-conductive region 123.SELECTED DRAWING: Figure 3
【課題】発生するサージ電圧を効果的に抑制することができる半導体モジュールを提供する。【解決手段】半導体モジュール100は、一方の面120aに、正極となるP側導電領域122、負極となるN側導電領域121及び出力がなされるO導電領域123が設けられた回路基板120と、O導電領域123に実装された第1の半導体チップ60と、P側導電領域122に実装された第2の半導体チップ70と、第1の半導体チップ60及び第2の半導体チップ70が実装されている回路基板120を囲むケース20及び開口部131が設けられた蓋130と、開口部131に挿入されたスナバ回路モジュール200と、を有し、スナバ回路モジュール200は、P側導電領域122、N側導電領域121、O導電領域123のうちの少なくとも2つと接続される。【選択図】 図3 |
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Bibliography: | Application Number: JP20190120317 |