SEMICONDUCTOR MODULE

• Main Authors: SAWADA KENICHI, EKUSA HIROSHI
• Format: Patent
• Language: English; Japanese
• Published: 14.01.2021
• Subjects: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS; BASIC ELECTRIC ELEMENTS; CONTROL OR REGULATION THEREOF; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERATION; SEMICONDUCTOR DEVICES

To provide a semiconductor module capable of effectively suppressing a generated surge voltage.SOLUTION: A semiconductor module 100 includes: a circuit board 120 having a P-side conductive region 122 to be a positive electrode, an N-side conductive region 121 to be a negative electrode, and an O-conductive region 123 to be an output, on one side surface 120a; a first semiconductor chip 60 mounted in the O-conductive region 123; a second semiconductor chip 70 mounted in the P-side conductive region 122; a cover 130 having a case 20 surrounding the circuit board 120 on which the first semiconductor chip 60 and the second semiconductor chip 70 are mounted, and an opening 131; and a snubber circuit module 200 inserted in the opening 131. The snubber circuit module 200 is connected to at least two of the P-side conductive region 122, the N-side conductive region 121 and the O-conductive region 123.SELECTED DRAWING: Figure 3 【課題】発生するサージ電圧を効果的に抑制することができる半導体モジュールを提供する。【解決手段】半導体モジュール１００は、一方の面１２０ａに、正極となるＰ側導電領域１２２、負極となるＮ側導電領域１２１及び出力がなされるＯ導電領域１２３が設けられた回路基板１２０と、Ｏ導電領域１２３に実装された第１の半導体チップ６０と、Ｐ側導電領域１２２に実装された第２の半導体チップ７０と、第１の半導体チップ６０及び第２の半導体チップ７０が実装されている回路基板１２０を囲むケース２０及び開口部１３１が設けられた蓋１３０と、開口部１３１に挿入されたスナバ回路モジュール２００と、を有し、スナバ回路モジュール２００は、Ｐ側導電領域１２２、Ｎ側導電領域１２１、Ｏ導電領域１２３のうちの少なくとも２つと接続される。【選択図】 図３