SEMICONDUCTOR STORAGE DEVICE

To provide a semiconductor storage device capable of improving operation reliability.SOLUTION: A semiconductor storage device of an embodiment comprises: a first conductive layer laminated in a Z direction and extending in an X direction; second and third conductive layers laminated in the Z directi...

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Main Authors NAKATSUKA KEISUKE, KATSUMATA RYUTA, SHIMOJO YOSHIRO, KUBOTA YOSHITAKA, UCHIUMI TETSUAKI
Format Patent
LanguageEnglish
Japanese
Published 24.09.2020
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Summary:To provide a semiconductor storage device capable of improving operation reliability.SOLUTION: A semiconductor storage device of an embodiment comprises: a first conductive layer laminated in a Z direction and extending in an X direction; second and third conductive layers laminated in the Z direction and arranged separated from the first conductive layer in a Y direction; a contact plug CP2 extending in the Z direction; a memory trench MST extending in the Z direction between the second conductive layer and the third conductive layer, continuously provided around the contact plug, and surrounding a first region in which the contact plug is arranged; and a second region separating from the first region in the X direction and including a memory pillar MP penetrating the first conductive layer in the Z direction. The second conductive layer extends between the first region and the second region in the X direction, further extends in the Y direction, and is connected to the first conductive layer. The third conductive layer extends in the X direction on the side opposite to the second region of the first region, further extends in the Y direction, and is connected to the first conductive layer.SELECTED DRAWING: Figure 20 【課題】動作信頼性を向上させることが可能な半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置は、Z方向に積層され、X方向に延伸する第1導電層と、Z方向に積層されX方向に延伸し、Y方向に第1導電層と離れて配置された第2及び第3導電層と、Z方向に延伸するコンタクトプラグCP2と、第2導電層と第3導電層間でZ方向に延伸し、コンタクトプラグの周囲に連続的に設けられ、コンタクトプラグが配置された第1領域を囲むメモリトレンチMSTと、第1領域とX方向に離れ、第1導電層をZ方向に貫通するメモリピラーMPを含む第2領域とを備える。第2導電層は、第1領域と第2領域との間でX方向に延伸し、さらにY方向に延伸して第1導電層と接続され、第3導電層は、第1領域の第2領域と反対側でX方向に延伸し、さらにY方向に延伸して第1導電層と接続される。【選択図】図20
Bibliography:Application Number: JP20190055071