MEMORY SYSTEM

To provide a memory system capable of suppressing decrease in operation speed.SOLUTION: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller for controlling the non-volatile memory chip. When reading out data from the non-volatile memory chip...

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Bibliographic Details
Main Authors SUZUKI RIKI, KOJIMA YOSHIHISA, NISHIKAWA TAKU, MARIE GRACE ISABEL ANGELES SIA
Format Patent
LanguageEnglish
Japanese
Published 24.09.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:To provide a memory system capable of suppressing decrease in operation speed.SOLUTION: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller for controlling the non-volatile memory chip. When reading out data from the non-volatile memory chip, the memory controller is configured to: instruct the non-volatile memory chip to perform a sensing operation to sense the data from the memory cell array, estimate a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller; and instruct the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.SELECTED DRAWING: Figure 15 【課題】動作速度の低下を抑制することが可能なメモリシステムを提供する。【解決手段】メモリシステムは、メモリセルアレイを備える不揮発性メモリチップと、前記不揮発性メモリチップを制御するメモリコントローラと、を備え、前記メモリコントローラは、前記不揮発性メモリチップからデータを読み出す場合、前記不揮発性メモリチップに、前記メモリセルアレイから前記データをセンスするセンス動作を指示し、前記不揮発性メモリチップから前記メモリコントローラに前記データが転送可能になる時刻を推定し、前記推定された時刻以降に、前記不揮発性メモリチップに、前記データを前記メモリコントローラに転送する転送動作を指示する。【選択図】 図１５
Bibliography:Application Number: JP20190052879