JUNCTION FIELD EFFECT TRANSISTOR

• Main Authors: TAKADA OSAMU, KITAHARA HIROYOSHI, TERADA NAOZUMI, INODO HIDEKAZU
• Format: Patent
• Language: English; Japanese
• Published: 10.09.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a junction field effect transistor capable of reducing noise.SOLUTION: The junction field effect transistor comprises: a first conductivity-type first semiconductor layer; an element isolation insulator provided at an upper layer portion of the first semiconductor layer and partitioning the active area; a second conductivity-type second semiconductor layer provided on the first semiconductor layer in the active area, and having an edge portion in a first direction separated from the element isolation insulator; a second conductivity-type source layer provided on the second semiconductor layer and having an impurity concentration higher than an impurity concentration of the second semiconductor layer; a second conductivity-type drain layer provided on the second semiconductor layer, separated from the source layer in a second direction intersecting with the first direction, and having an impurity concentration higher than the impurity concentration of the second semiconductor layer; and a first conductivity-type gate layer provided on the second semiconductor layer, disposed between the source layer and the drain layer, and separated from the source layer and the drain layer.SELECTED DRAWING: Figure 2 【課題】ノイズを低減可能な接合型電界効果トランジスタを提供する。【解決手段】接合型電界効果トランジスタは、第１導電形の第１半導体層と、前記第１半導体層の上層部分に設けられ、アクティブエリアを区画する素子分離絶縁体と、前記アクティブエリア内における前記第１半導体層上に設けられ、第２導電形であり、第１方向の端部が前記素子分離絶縁体から離隔した第２半導体層と、前記第２半導体層上に設けられ、前記第２導電形であり、不純物濃度が前記第２半導体層の不純物濃度よりも高いソース層と、前記第２半導体層上に設けられ、前記ソース層から前記第１方向に対して交差した第２方向に離隔し、前記第２導電形であり、不純物濃度が前記第２半導体層の不純物濃度よりも高いドレイン層と、前記第２半導体層上に設けられ、前記ソース層と前記ドレイン層との間に配置され、前記ソース層及び前記ドレイン層から離隔し、前記第１導電形であるゲート層と、を備える。【選択図】図２