SEMICONDUCTOR STORAGE DEVICE

• Main Authors: NAKATSUKA KEISUKE, MOMO NOBUYUKI, ARAI FUMITAKA, HOSOYA KEIJI, FUJIMATSU MOTOHIKO
• Format: Patent
• Language: English; Japanese
• Published: 10.09.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To suppress an increase in a chip area.SOLUTION: According to an embodiment, a semiconductor storage device includes: a first semiconductor layer 31 including first to third portions (HPR1 to HPR3) arranged side by side in a first direction and having different positions with each other in a second direction; a conductive layer 39 including a fourth portion 39a extending in the second direction and a fifth portion 39b extending in the first direction; a first insulation layer 38 provided between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug CSGD connected to the fourth portion; a second contact plug CBL connected to the first semiconductor layer in a region in which the first insulation layer is formed; first wiring CWL; and a first memory cell storing information between the first semiconductor layer and the first wiring.SELECTED DRAWING: Figure 10 【課題】チップ面積の増加を抑制する。【解決手段】実施形態によれば、半導体記憶装置は、第１方向に並んで配置され、第２方向における位置が互いに異なる第１乃至第３部分（ＨＰＲ１〜ＨＰＲ３）を含む第１半導体層３１と、第２方向に延伸する第４部分３９ａ及び第１方向に延伸する第５部分３９ｂを含む導電層３９と、第４部分と第１半導体層との間、及び第５部分と第１半導体層との間に設けられた第１絶縁層３８と、第４部分と接続された第１コンタクトプラグＣＳＧＤと、第１絶縁層が形成されている領域内で第１半導体層と接続される第２コンタクトプラグＣＢＬと、第１配線ＣＷＬと、第１半導体層と第１配線との間で情報を記憶する第１メモリセルとを含む。【選択図】図１０