SEMICONDUCTOR DEVICE

To provide a semiconductor device capable of suppressing positional deviation of a connection lead.SOLUTION: A semiconductor device A1 comprises: a semiconductor element including a first electrode and a second electrode which are disposed on faces mutually directed to opposite sides in a (z) direct...

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Bibliographic Details
Main Authors ISE KOTA, SAITO MITSUTOSHI
Format Patent
LanguageEnglish
Japanese
Published 04.06.2020
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Summary:To provide a semiconductor device capable of suppressing positional deviation of a connection lead.SOLUTION: A semiconductor device A1 comprises: a semiconductor element including a first electrode and a second electrode which are disposed on faces mutually directed to opposite sides in a (z) direction; a first lead to which the first electrode is joined; a second lead which is conducted with the second electrode; and a connection lead 3 including an element connection part 31 which is joined to the second electrode, and a lead connection part 32 which is joined to the second lead 2 by a solder 9. The lead connection part 32 includes: a lead connection part first face 321 which is directed to the side of the semiconductor element in a (y) direction; and a lead connection part second face 322 which is directed to an opposite side thereof. The second lead 2 includes a connection part recess 24 which includes a recess first side face 242 opposed to the lead connection part second face 322 and opened at the side of the semiconductor element. An area of a second contact region S2 between the lead connection part second face 322 and the solder 9 is larger than an area of a first contact region S1 between the lead connection part first face 321 and the solder 9.SELECTED DRAWING: Figure 10 【課題】接続リードの位置ずれを抑制できる半導体装置を提供する。【解決手段】半導体装置A1において、z方向において互いに反対側を向く面にそれぞれ配置された第1電極および第2電極を有する半導体素子と、第1電極が接合された第1リードと、第2電極と導通する第2リード2と、第2電極に接合された素子接続部31、および、はんだ9によって第2リード2に接合されたリード接続部32を有する接続リード3とを備えた。リード接続部32は、y方向において、半導体素子側を向くリード接続部第1面321と、その反対側を向くリード接続部第2面322とを備える。第2リード2は、リード接続部第2面322に対向する凹部第1側面242を有し、かつ、半導体素子側が開放された接続部凹部24を備える。リード接続部第2面322とはんだ9との第2接触領域S2の面積が、リード接続部第1面321とはんだ9との第1接触領域S1の面積より大きい。【選択図】図10
Bibliography:Application Number: JP20180224872