SEMICONDUCTOR INTEGRATED CIRCUIT

• Main Author: YAMAJI MASAHARU
• Format: Patent
• Language: English; Japanese
• Published: 04.06.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor integrated circuit capable of achieving high noise immunity in an HVIC without increasing a chip area.SOLUTION: A semiconductor integrated circuit includes a semiconductor substrate 10 of a first conductivity type, a second well region 4 of a second conductivity type, which is provided on the semiconductor substrate 10 and to which a first potential is applied, a second well region 5 of the first conductivity type, which is provided on the first well region 4 and to which a second potential lower than the first potential is applied, a main electrode region 14 provided above the first well region 4 and separated from the second well region 5 and to which a second potential is applied, a first buried layer 71 of the second conductive type, which is locally buried under the second well region 5, and a second buried layer 72 of the second conductive type, which is separated from the first buried layer 71 and locally buried under the main electrode region 14.SELECTED DRAWING: Figure 4 【課題】ＨＶＩＣにおいて、チップ面積を大きくせずに高ノイズ耐量化を図ることができる半導体集積回路を提供する。【解決手段】第１導電型の半導体基体１０と、半導体基体１０の上部に設けられ、第１電位が印加される第２導電型の第１ウェル領域４と、第１ウェル領域４の上部に設けられ、第１電位よりも低い第２電位が印加される第１導電型の第２ウェル領域５と、第１ウェル領域４の上部に第２ウェル領域５と離間して設けられ、第２電位が印加される主電極領域１４と、第２ウェル領域５の下に局所的に埋め込まれた第２導電型の第１埋め込み層７１と、第１埋め込み層７１と離間して、主電極領域１４の下に局所的に埋め込まれた第２導電型の第２埋め込み層７２とを備える。【選択図】図４