HIGH RESISTIVITY SOI WAFER AND MANUFACTURING METHOD OF THE SAME

• Main Authors: IGOR PEIDOUS, SRIKANTH KOMMU, WANG GAN, SHAWN G THOMAS
• Format: Patent
• Language: English; Japanese
• Published: 14.05.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a high resistivity single crystal semiconductor support structure which is used for manufacturing a SOI structure.SOLUTION: A support structure comprises an intermediate semiconductor layer 40 provided between a support substrate 32 and an embedded oxide layer 34 having a positive charge 36. The intermediate semiconductor layer includes a polycrystalline structure, an amorphous structure, a nanocrystal structure, or a single crystal structure, and includes a material selected from the group consisting of SiGex, SiC, SiGeSn, SiGeSnC, GeSn, a group III A nitride, and a metal oxide, and an arbitrary combination of them.SELECTED DRAWING: Figure 3 【課題】ＳＯＩ構造の製造に利用される高抵抗率単結晶半導体支持構造を提供する。【解決手段】支持構造は、支持基板３２と正電荷３６を有する埋め込み酸化物層３４との間に設けられた中間半導体層４０を備えている。中間半導体層は、多結晶構造、アモルファス構造、ナノ結晶構造または単結晶構造を有し、Ｓｉ１−ｘＧｅｘ、Ｓｉ１−ｘＣｘ、Ｓｉ１−ｘ−ｙＧｅｘＳｎｙ、Ｓｉ１−ｘ−ｙ−ｚＧｅｘＳｎｙＣｚ、Ｇｅ１−ｘＳｎｘ、ＩＩＩＡ族窒化物、金属酸化物およびこれらの任意の組合せから成る群から選択される材料を含む。【選択図】図３