SEMICONDUCTOR STORAGE DEVICE

• Main Authors: MOMO NOBUYUKI, ARAI FUMITAKA, HOSOYA KEIJI
• Format: Patent
• Language: English; Japanese
• Published: 07.05.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

To reduce power consumption.SOLUTION: According to an embodiment, a semiconductor storage device includes: a first wiring BL; a second wiring SL; a third wiring SG; a fourth wiring WL; a fifth wiring TG; a semiconductor layer 46 in which one end is located between the fourth wiring and the fifth wiring and the other end is connected to the first wiring; a memory cell MC; a conductive layer in which one end is connected to the second wiring and the other end is connected to the semiconductor layer; a first insulation layer 45 provided so as to extend between the third wiring and the semiconductor layer, between the fourth wiring and the semiconductor layer, and between the fifth wiring and the conductive layer; an oxide semiconductor layer 44 provided so as to extend between the fourth wiring and the first insulation layer and between the fifth wiring and the first insulation layer; and a second insulation layer 43 provided so as to extend between the fourth wiring and the oxide semiconductor layer and between the fifth wiring and the oxide semiconductor layer.SELECTED DRAWING: Figure 5 【課題】消費電力を低減する。【解決手段】実施形態によれば、半導体記憶装置は、第１配線ＢＬと、第２配線ＳＬと、第３配線ＳＧと、第４配線ＷＬと、第５配線ＴＧと、一端が第４配線と第５配線の間に位置し、他端が第１配線に接続された半導体層４６と、メモリセルＭＣと、一端が第２配線に接続され、他端が半導体層に接続された導電層と、第３配線と半導体層との間、第４配線と半導体層の間、及び第５配線と導電層の間に延在するように設けられた第１絶縁層４５と、第４配線と第１絶縁層との間、及び第５配線と第１絶縁層との間に延在するように設けられた酸化物半導体層４４と、第４配線と酸化物半導体層との間、及び第５配線と酸化物半導体層の間に延在するように設けられた第２絶縁層４３と、を含む。【選択図】図５