METHOD OF MANUFACTURING DEVICE AND DEVICE

To provide a semiconductor device that can achieve high performance, mass productivity and cost reduction.SOLUTION: A semiconductor device comprises: a first semiconductor substrate that has a transfer Tr, a reset Tr and an amplification Tr arranged on a pixel array; and a second semiconductor subst...

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Bibliographic Details
Main Authors TAKAHASHI HIROSHI, SHOJI REIJIRO, UMEBAYASHI HIROSHI
Format Patent
LanguageEnglish
Japanese
Published 09.04.2020
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Summary:To provide a semiconductor device that can achieve high performance, mass productivity and cost reduction.SOLUTION: A semiconductor device comprises: a first semiconductor substrate that has a transfer Tr, a reset Tr and an amplification Tr arranged on a pixel array; and a second semiconductor substrate that has a logic circuit processing signals. The first semiconductor substrate and the second semiconductor substrate are laminated so that a first multilayer wiring layer and a second multilayer wiring layer are opposed to each other. At least one or more wirings at a side closest to the second semiconductor substrate of the first multilayer wiring layer and at least one or more wirings at a side closest to the first semiconductor substrate of the second multilayer wiring layer are directly bonded with each other.SELECTED DRAWING: Figure 3 【課題】高性能化、且つ量産性、コスト低減を図った半導体装置を提供する。【解決手段】画素アレイに配置された、転送Tr、リセットTr、及び、増幅Trを有する第1の半導体基板と、信号処理を行うロジック回路を有する第2の半導体基板とを有する。第1の半導体基板と第2の半導体基板とは、第1の多層配線層と第2の多層配線層とが向かい合うように積層され、第1の多層配線層の最も第2の半導体基板側の少なくとも1つ以上の配線と、第2の多層配線層の最も第1の半導体基板側の少なくとも1つ以上の配線とが直接接合されている。【選択図】図3
Bibliography:Application Number: JP20190233338