SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC EQUIPMENT

• Main Authors: OOKA YUTAKA, KOMAI HISANORI, OSADA MASAYA, OIKAMI TAKASHI, IWAMOTO ISATO, SASAKI NAOTO, OGAWA NAOKI
• Format: Patent
• Language: English; Japanese
• Published: 26.03.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION; SEMICONDUCTOR DEVICES

To further reduce a size of a semiconductor device.SOLUTION: A semiconductor device comprises: a first semiconductor substrate where a pixel region is formed; a second semiconductor substrate where a logic circuit for processing a pixel signal is formed; a through electrode passing through the second semiconductor substrate; a rewiring electrically connecting the through electrode and an electrode part to each other; a dummy wiring formed in the same layer as the rewiring; and a protection substrate protecting an on-chip lens. The protection substrate is in a cavityless structure and is connected with the first semiconductor substrate, a wiring layer of the first semiconductor substrate includes a first wiring layer, a wiring layer of the second semiconductor substrate includes a second wiring layer, the first semiconductor substrate and the second semiconductor substrate have a plurality of coupling regions where the first wiring layer and the second wiring layer are connected to each other through metal coupling, and a length in a plane direction of the dummy wiring is longer than that of one coupling region, and the dummy wiring is disposed in a length in which the dummy wiring overlaps with two coupling regions at least in part. A technique of the present disclosure is applicable, for instance, to a packaged solid state image pickup device or the like.SELECTED DRAWING: Figure 14 【課題】半導体装置をより小型化する。【解決手段】半導体装置は、画素領域が形成された第１の半導体基板と、画素信号を処理するロジック回路が形成された第２の半導体基板と、第２の半導体基板を貫通する貫通電極と、貫通電極と電極部とを電気的に接続する再配線と、再配線と同一層に形成されたダミー配線と、オンチップレンズを保護する保護基板とを備え、保護基板は、キャビティレス構造で第１の半導体基板と接続されており、第１の半導体基板の配線層は第１配線層を含み、第２の半導体基板の配線層は第２配線層を含み、第１の半導体基板と第２の半導体基板は、第１配線層と第２配線層とを金属結合により接続した結合領域を複数有しており、ダミー配線の平面方向の長さが、結合領域の１つよりも長く、２つの結合領域の少なくとも一部と重なる長さで配置される。本開示の技術は、例えば、パッケージ化された固体撮像装置等に適用できる。【選択図】図１４