SEMICONDUCTOR DEVICE

• Main Authors: HASHIMOTO CHIEMI, YAYAMA KOSUKE, MATSUZAKI TOMOKAZU
• Format: Patent
• Language: English; Japanese
• Published: 05.03.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MEASURING; MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER,MECHANICAL EFFICIENCY, OR FLUID PRESSURE; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

To solve a problem in which a polycrystalline silicon resistor has a large resistance variation after the end of a mold package process, and in order to enable high-precision trimming, it is desired to realize a resistor that is hardly affected by stress and temperature fluctuation generated in a substrate by the mold package process.SOLUTION: A semiconductor includes a repeating pattern of a first conductive layer 31 in which a resistance element is formed in a plurality of wiring layers, and that is formed in a first wiring layer, a second conductive layer 32 formed on a second wiring layer, and an interlayer conductive layer 33 connecting the first conductive layer 31 and the second conductive layer 32, and the interlayer conductive layer is made of a plurality of types of materials.SELECTED DRAWING: Figure 5 【課題】多結晶シリコン抵抗はモールドパッケージプロセス終了後の抵抗変動率が大きい。高精度なトリミングを可能とするために、モールドパッケージプロセスにより基板に生じる応力の影響及び温度変動の影響をほとんど受けない抵抗の実現が望まれる。【解決手段】抵抗素子は複数の配線層に形成され、第１の配線層に形成される第１導電層３１、第２の配線層に形成される第２導電層３２及び第１導電層３１と第２導電層３２とを接続する層間導電層３３の繰り返しパターンを有し、層間導電層は複数種類の材質で構成されている。【選択図】図５