PROCESSOR, CONTROL METHOD OF MULTI-LEVEL CACHE MEMORY, AND CONTROL PROGRAM OF MULTI-LEVEL CACHE MEMORY

To provide a processor capable of suppressing electrical power consumption while maintaining or improving application execution performance.SOLUTION: The processor includes: a cache memory having multiple layers; and a determination part that determines whether or not the cache memory in the first l...

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Main Authors ONISHI TAKAYUKI, OMORI YUYA, SATO MASAYUKI, IWASAKI HIROE, SHIMIZU ATSUSHI, KOBAYASHI HIROAKI, EGAWA RYUSUKE
Format Patent
LanguageEnglish
Japanese
Published 27.02.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:To provide a processor capable of suppressing electrical power consumption while maintaining or improving application execution performance.SOLUTION: The processor includes: a cache memory having multiple layers; and a determination part that determines whether or not the cache memory in the first layer should be enabled on the basis of the contribution of the cache memory of the first layer, which is calculated on the basis of value based on the power efficiency, a state of the cache memory in the first layer included in the multiple layers, and the state of the cache memory of a second layer different from the first layer included in the multiple layers.SELECTED DRAWING: Figure 1 【課題】アプリケーションの実行性能を維持又は向上させつつ、消費電力を抑制すること。【解決手段】プロセッサは、複数の階層からなるキャッシュメモリと、電力効率と、前記複数の階層に含まれる第一の階層のキャッシュメモリの状態と前記複数の階層に含まれる前記第一の階層とは異なる第二の階層のキャッシュメモリの状態とに基づく値と、に基づいて算出される、前記第一の階層のキャッシュメモリの貢献度に基づいて、前記第一の階層のキャッシュメモリを有効化するか否かを判定する判定部と、を備える。【選択図】図１
Bibliography:Application Number: JP20180156654