CLOCK WAVE PEAK VALUE BOOST CIRCUIT
To provide a clock wave peak value boost circuit capable of operating at a low voltage.SOLUTION: In a clock wave peak value boost circuit 100, a depletion type NMOS transistor 101 is so configured that a source is connected to a node N11, a drain is connected to a power supply terminal 1, and a gate...
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13.02.2020
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Abstract | To provide a clock wave peak value boost circuit capable of operating at a low voltage.SOLUTION: In a clock wave peak value boost circuit 100, a depletion type NMOS transistor 101 is so configured that a source is connected to a node N11, a drain is connected to a power supply terminal 1, and a gate is connected to an input terminal 10. An NMOS transistor 102 is so configured that a source is connected to a GND terminal 2, a drain is connected to a node N11, and a gate is connected to an input terminal 11. A depletion type NMOS transistor 104 is so configured that a source is connected to a node N12, a drain is connected to the power supply terminal 1, and a gate is connected to the input terminal 11. A capacitor 103 is connected between the nodes N11 and the nodes N12. A PMOS transistor 105 is so configured that a source is connected to the node N12, a drain is connected to the output terminal 12, and a gate is connected to the input terminal 11.SELECTED DRAWING: Figure 1
【課題】低い電圧で動作が可能なクロック波高値ブースト回路を提供する。【解決手段】クロック波高値ブースト回路100において、ディプレッション型NMOSトランジスタ101は、ソースがノードN11に接続され、ドレインが電源端子1に接続され、ゲートが入力端子10に接続されている。NMOSトランジスタ102は、ソースがGND端子2に接続され、ドレインがノードN11に接続され、ゲートが入力端子11に接続されている。ディプレッション型NMOSトランジスタ104は、ソースがノードN12に接続され、ドレインが電源端子1に接続され、ゲートが入力端子11に接続されている。コンデンサ103は、ノードN11とノードN12の間に接続されている。PMOSトランジスタ105は、ソースがノードN12に接続され、ドレインが出力端子12に接続され、ゲートが入力端子11に接続されている。【選択図】図1 |
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AbstractList | To provide a clock wave peak value boost circuit capable of operating at a low voltage.SOLUTION: In a clock wave peak value boost circuit 100, a depletion type NMOS transistor 101 is so configured that a source is connected to a node N11, a drain is connected to a power supply terminal 1, and a gate is connected to an input terminal 10. An NMOS transistor 102 is so configured that a source is connected to a GND terminal 2, a drain is connected to a node N11, and a gate is connected to an input terminal 11. A depletion type NMOS transistor 104 is so configured that a source is connected to a node N12, a drain is connected to the power supply terminal 1, and a gate is connected to the input terminal 11. A capacitor 103 is connected between the nodes N11 and the nodes N12. A PMOS transistor 105 is so configured that a source is connected to the node N12, a drain is connected to the output terminal 12, and a gate is connected to the input terminal 11.SELECTED DRAWING: Figure 1
【課題】低い電圧で動作が可能なクロック波高値ブースト回路を提供する。【解決手段】クロック波高値ブースト回路100において、ディプレッション型NMOSトランジスタ101は、ソースがノードN11に接続され、ドレインが電源端子1に接続され、ゲートが入力端子10に接続されている。NMOSトランジスタ102は、ソースがGND端子2に接続され、ドレインがノードN11に接続され、ゲートが入力端子11に接続されている。ディプレッション型NMOSトランジスタ104は、ソースがノードN12に接続され、ドレインが電源端子1に接続され、ゲートが入力端子11に接続されている。コンデンサ103は、ノードN11とノードN12の間に接続されている。PMOSトランジスタ105は、ソースがノードN12に接続され、ドレインが出力端子12に接続され、ゲートが入力端子11に接続されている。【選択図】図1 |
Author | UTSUNOMIYA FUMIYASU |
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DocumentTitleAlternate | クロック波高値ブースト回路 |
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Snippet | To provide a clock wave peak value boost circuit capable of operating at a low voltage.SOLUTION: In a clock wave peak value boost circuit 100, a depletion type... |
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SubjectTerms | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
Title | CLOCK WAVE PEAK VALUE BOOST CIRCUIT |
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