TRANCEIMPEDANCE AMPLIFIER
To provide a TIA in which linearity is improved.SOLUTION: A transistor M1 is connected between an input terminal 10a of a TIA core 10 and an input terminal 20a of a dummy TIA 20, and the value of resistance between the input terminal 10a and the input terminal 20a changes according to the amplitude...
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Main Author | |
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Format | Patent |
Language | English Japanese |
Published |
09.01.2020
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a TIA in which linearity is improved.SOLUTION: A transistor M1 is connected between an input terminal 10a of a TIA core 10 and an input terminal 20a of a dummy TIA 20, and the value of resistance between the input terminal 10a and the input terminal 20a changes according to the amplitude value of a voltage Vtiaout generated by the TIA core 10, a voltage Vdiff1 generated by the VGA30, or a voltage Vdiff2 generated by a buffer amplifier 40. A transistor M2 is connected between the input terminal 10a of the TIA core 10 and a ground, and controls the current value of an electric current flowing from the input terminal 10a to the ground according to the magnitude of offset of the voltage Vdiff1 or Vdiff2. A bias voltage (voltage Vb2) of the same magnitude as a bias voltage (voltage Vb1) applied to the input terminal 10a is applied to the input terminal 20a.SELECTED DRAWING: Figure 1
【課題】線形性が改善されたTIAを提供する。【解決手段】トランジスタM1は、TIAコア10の入力端子10aとダミーTIA20の入力端子20aとの間に接続され、TIAコア10が生成する電圧Vtiaout、VGA30が生成する電圧Vdiff1又はバッファアンプ40が生成する電圧Vdiff2の振幅値に応じて入力端子10aと入力端子20aとの間の抵抗値が変化する。トランジスタM2は、TIAコア10の入力端子10aとグランドとの間に接続され、電圧Vdiff1又は電圧Vdiff2のオフセットの大きさに応じて入力端子10aからグランドへ流れる電流の電流値を制御する。入力端子20aには、入力端子10aに与えられているバイアス電圧(電圧Vb1)と同じ大きさのバイアス電圧(電圧Vb2)が与えられている。【選択図】図1 |
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Bibliography: | Application Number: JP20180122921 |