SEMICONDUCTOR DEVICE

To provide a semiconductor device in which reliability of a transistor is improved.SOLUTION: The semiconductor device has a transistor that includes: a gate electrode provided on a substrate; a gate insulating film provided on the gate electrode; an oxide semiconductor layer provided on the gate ele...

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Main Authors KANEKO TOSHITERU, TODA TATSUYA, SAKAMOTO MICHIAKI, OKADA TAKASHI, TSUBUKI MASASHI
Format Patent
LanguageEnglish
Japanese
Published 12.12.2019
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Summary:To provide a semiconductor device in which reliability of a transistor is improved.SOLUTION: The semiconductor device has a transistor that includes: a gate electrode provided on a substrate; a gate insulating film provided on the gate electrode; an oxide semiconductor layer provided on the gate electrode via the gate insulating film; a source electrode and a drain electrode provided on the oxide semiconductor layer; a protection film provided on the source electrode and the drain electrode; and a conductive layer provided on the protection film and superposed with the oxide semiconductor layer. In the protection film, a first silicon oxide film and a first silicon nitride film are laminated, and the first silicon oxide film is in contact with the oxide semiconductor layer. In the gate insulating film, a second silicon nitride film and a second silicon oxide film are laminated, and the second silicon oxide film is in contact with the oxide semiconductor layer. In a plan view, the oxide semiconductor layer has a first region located between the source electrode and the drain electrode, and a part of the first region is superposed with the conductive layer.SELECTED DRAWING: Figure 1B 【課題】トランジスタの信頼性が向上した半導体装置を提供する。【解決手段】半導体装置は、基板上に設けられたゲート電極と、ゲート電極上に設けられたゲート絶縁膜と、ゲート電極上にゲート絶縁膜を介して設けられる酸化物半導体層と、酸化物半導体層上に設けられたソース電極及びドレイン電極と、ソース電極及びドレイン電極上に設けられた保護膜と、保護膜上に設けられ、酸化物半導体層と重畳する導電層と、を含むトランジスタを有し、保護膜は、第1酸化シリコン膜と第1窒化シリコン膜とが積層され、第1酸化シリコン膜は、酸化物半導体層と接しており、ゲート絶縁膜は、第2窒化シリコン膜と第2酸化シリコン膜とが積層され、第2酸化シリコン膜は、酸化物半導体層と接しており、平面視において、酸化物半導体層は、ソース電極とドレイン電極との間に位置する第1領域を有し、第1領域の一部は、導電層と重畳する。【選択図】図1B
Bibliography:Application Number: JP20180108623