SEMICONDUCTOR DEVICE

• Main Authors: EMA TAIJI, YASUDA MAKOTO
• Format: Patent
• Language: English; Japanese
• Published: 28.11.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

To provide a semiconductor device capable of further reducing power consumption.SOLUTION: A semiconductor device 100 comprises: a first semiconductor region 114s having lower concentration than a source region 115s and including a first conductivity type impurity; a second semiconductor region 114d in which concentration of the first conductivity type impurity is lower than a drain region 115d; a channel region 113 provided between the first semiconductor region 114s and the second semiconductor region 114d; and a third semiconductor region 112 provided below the channel region 113 and including a second conductivity type impurity having higher concentration than the channel region 113. When an electric charge is injected into a sidewall insulation film 120d, a semiconductor substrate 101 is grounded, a first voltage higher than a ground potential is applied to a gate electrode 117, a second voltage hither than the ground potential is applied to the drain region 115d, and a third voltage higher than the ground potential and lower than the first voltage and the second voltage is applied to the source region 115s.SELECTED DRAWING: Figure 1 【課題】消費電力を更に低減することができる半導体装置を提供する。【解決手段】半導体装置１００は、ソース領域１１５ｓよりも低濃度で第１導電型の不純物を含む第１の半導体領域１１４ｓと、第１導電型の不純物の濃度がドレイン領域１１５ｄよりも低い第２の半導体領域１１４ｄと、第１の半導体領域１１４ｓと第２の半導体領域１１４ｄとの間に設けられたチャネル領域１１３と、チャネル領域１１３の下方に設けられ、チャネル領域１１３よりも高濃度の第２導電型の不純物を含む第３の半導体領域１１２と、を有する。サイドウォール絶縁膜１２０ｄへの電荷の注入時に、半導体基板１０１が接地され、ゲート電極１１７に接地電位よりも高い第１の電圧が印加され、ドレイン領域１１５ｄに接地電位よりも高い第２の電圧が印加され、ソース領域１１５ｓに接地電位よりも高く、第１の電圧及び第２の電圧よりも低い第３の電圧が印加される。【選択図】図１