SEMICONDUCTOR DEVICE

• Main Authors: WATANABE NAOTAKE, MIZUTANI ASAMI, SEKIYA HIRONORI, ITO HIROAKI, ICHIKURA YUTA, TADA NOBUMITSU, KURI YUUJI, IIO HISATAKA, TASHIRO SHOTA
• Format: Patent
• Language: English; Japanese
• Published: 21.11.2019
• Subjects: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS; BASIC ELECTRIC ELEMENTS; CONTROL OR REGULATION THEREOF; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERATION; SEMICONDUCTOR DEVICES

To provide a semiconductor device that can reduce a difference of a load current for each of a plurality of semiconductor elements due to impedance of a wiring pattern of a circuit board.SOLUTION: A semiconductor device 1 comprises a substrate 11 comprising: a plurality of semiconductor elements 9a-9h that have power supply side electrodes and load side electrodes; a plurality of power supply side terminals 52 that are connected to power supply; a plurality of load side terminals 42a, 42b that are connected to a load; power supply side conductive layers 51a, 51b that electrically connect between a plurality of power supply side terminals 52a, 52b and power supply side electrodes of the plurality of semiconductor elements 9 and that are constituted in a surface state; a load side conductive layer 41 that connects between the plurality of load side terminals and the load side electrodes of the plurality of semiconductor elements and that is constituted in a surface state; and an insulator layer that electrically isolates between the power supply side conductive layers and the load side conductive layer. The plurality of semiconductor elements are arranged on the substrate taking substantially the same distances from the plurality of power supply side terminals and the plurality of load side terminals.SELECTED DRAWING: Figure 1 【課題】回路基板の配線パターンのインピーダンスに起因する、複数の半導体素子ごとの負担電流の相違を軽減することができる半導体装置を提供する。【解決手段】半導体装置１は、電源側電極と負荷側電極と、を有する複数の半導体素子９ａ〜９ｈと、電源に接続される複数の電源側端子５２と、負荷に接続される複数の負荷側端子４２ａ、４２ｂと、複数の電源側端子５２ａ、５２ｂと複数の半導体素子９の電源側電極を電気的に接続する、面状に構成された電源側の導電層５１ａ、５１ｂと、複数の負荷側端子と複数の半導体素子の負荷側電極を電気的に接続する、面状に構成された負荷側の導電層４１と、電源側の導電層と負荷側の導電層とを電気的に絶縁する絶縁層と、を有する基板１１を備える。複数の半導体素子は、複数の電源側端子および複数の負荷側端子から略同等の距離で、基板上に配置される。【選択図】図１