ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE

• Main Author: OKAZAKI RYOHEI
• Format: Patent
• Language: English; Japanese
• Published: 24.10.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

To suppress deterioration of throughput of a processor.SOLUTION: An arithmetic processing device comprises: an instruction decoder that has K slots; first through fourth reservation stations (RS) having L (K>L>2) input ports; first/second RS dedicated first/second arithmetic units; third/fourth RS dedicated first/second load store (LS) units; and an allocation unit that allocates K instructions to any of the first through fourth RS. A first instruction that can be executed by the first/second arithmetic units and that cannot be executed by the first/second LS units is allocated to the first or second RS on the basis of a first allocation table, a second instruction that can be executed by the first/second LS units and that cannot be executed by the first/second arithmetic units is allocated to the third or fourth RS on the basis of a second allocation table, and a third instruction that can be executed by the first/second LS units and the first/second arithmetic units is allocated to any of the first through fourth RS on the basis of a third allocation table.SELECTED DRAWING: Figure 2 【課題】プロセッサのスループットの低下を抑制する。【解決手段】Ｋ個のスロットを有する命令デコーダと、Ｌ個（Ｋ＞Ｌ＞２）の入力ポート有する第１〜４リザベーションステーション（ＲＳ）と、第１／第２ＲＳ専用の第１／第２演算ユニットと、第３／第４ＲＳ専用の第１／第２ロードストア（ＬＳ）ユニットと、Ｋ個の命令を、第１〜４ＲＳのいずれかに割り振るアロケーションユニットを有する。第１／第２演算ユニットで実行でき、第１／第２のＬＳユニットで実行できない第１の命令は第１の割振りテーブルに基づいて第１または第２ＲＳに割振り、第１／第２ＬＳユニットで実行でき、第１／第２演算ユニットで実行できない第２の命令は第２の割振りテーブルに基づいて第３または第４のＲＳに割振り、第１／第２ＬＳユニットと第１／第２演算ユニットで実行できる第３の命令は第３の割振りテーブルに基づいて前記第１〜４のＲＳのいずれかに割振る。【選択図】図２