SEMICONDUCTOR STORAGE DEVICE

• Main Author: SATO JUNPEI
• Format: Patent
• Language: English; Japanese
• Published: 03.10.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor storage device that can be made fine.SOLUTION: A semiconductor storage device according to an embodiment includes: a substrate; a control circuit provided on the substrate and including a transistor; a first pad region including a pad above the substrate; a second pad region including a pad above the substrate; n wiring layers; and a first wiring region. The n wiring layers are n (n: a natural number equal to or larger than 3) wiring layers above the substrate, and the n wiring layers are positioned at mutually different heights from the substrate, the n wiring layers including wiring, respectively. The first wiring region is positioned between an end of the control circuit and an end of the substrate in a direction in which a first axis extends, and arranged side by side with the first pad region in a direction in which a second axis extends, and includes neither the transistor nor a contact connected to the substrate either, m (m: a natural number which is 3 or larger, and larger than n/2 and less than n) of the n wiring layers including wiring extending along the second axis.SELECTED DRAWING: Figure 3 【課題】微細化可能な半導体記憶装置を提供する。【解決手段】 実施形態の半導体記憶装置は、基板と、基板上に設けられ、トランジスタを含んだ制御回路と、基板の上方のパッドを含んだ第１パッド領域と、基板の上方のパッドを含んだ第２パッド領域と、ｎ個の配線層と、第１配線領域と、を含む。ｎ個の配線層は、基板の上方のｎ（ｎは３以上の自然数）個の配線層であって、ｎ個の配線層はｎ個の配線層は基板から互いに異なる高さに位置し、ｎ個の配線層の各々は配線を含む。第１配線領域は、第１軸の延びる方向において制御回路の端と基板との端との間に位置するとともに第２軸の延びる方向において第１パッド領域と並び、トランジスタを含まず、基板と接続されたコンタクトを含まず、ｎ個の配線層のうちのｍ（ｍは３以上且つｎ／２超且つｎ以下の自然数）個の配線層において第２軸に沿って延びる配線を含む。【選択図】 図３