SEMICONDUCTOR DEVICE

To provide a semiconductor device capable of supplying a uniform voltage to a plurality of semiconductor chips laminated on a substrate.SOLUTION: A semiconductor device comprises a laminate including a plurality of semiconductor chips arranged on a base member, a first conductor provided on the lami...

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Bibliographic Details
Main Authors KAWASAKI KAZUSHIGE, KOYANAGI MASARU, ITO MIKIHIKO, TSUKIYAMA KEISHI
Format Patent
LanguageEnglish
Japanese
Published 26.09.2019
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Summary:To provide a semiconductor device capable of supplying a uniform voltage to a plurality of semiconductor chips laminated on a substrate.SOLUTION: A semiconductor device comprises a laminate including a plurality of semiconductor chips arranged on a base member, a first conductor provided on the laminate, a second conductor provided on an upper surface of the base member, and a connection conductor connecting the first and second conductors. The plurality of semiconductor chips respectively include a through electrode reaching from a rear surface to an element surface. The laminate includes through electrodes of the plurality of semiconductor chips, and a common terminal electrically connected to each semiconductor chip. The common terminal includes a lower end provided on a lower surface of the semiconductor chip positioned at the lowermost stage among the plurality of semiconductor chips and an upper end provided on an upper surface of the semiconductor chip positioned at the uppermost stage. The first conductor is connected to the upper end of the common terminal. The second conductor is connected to the first conductor via the connector conductor, and electrically connected to the lower end of the common terminal.SELECTED DRAWING: Figure 1 【課題】基板上に積層された複数の半導体チップに均一な電圧を供給可能な半導体装置を提供する。【解決手段】半導体装置は、ベース部材上に配置された複数の半導体チップを含む積層体と、前記積層体上に設けられた第1導体と、前記ベース部材の上面に設けられた第2導体と、前記第1導体と前記第2導体とを接続する接続導体と、を備える。前記複数の半導体チップは、裏面から素子面へ至る貫通電極をそれぞれ含む。前記積層体は、前記複数の半導体チップの前記貫通電極を含み、各半導体チップに電気的に接続された共通端子を有する。前記共通端子は、前記複数の半導体チップのうちの最下段に位置する半導体チップの下面に設けられた下端と、最上段に位置する半導体チップの上面に設けられた上端と、を有する。前記第1導体は、前記共通端子の上端に接続され、前記第2導体は、前記接続導体を介して前記第1導体に接続されると共に、前記共通端子の下端に電気的に接続される。【選択図】図1
Bibliography:Application Number: JP20180053315