SEMICONDUCTOR STORAGE DEVICE

To provide a semiconductor storage device capable of improving product performance and reliability.SOLUTION: A semiconductor storage device according to an embodiment comprises: a substrate; a laminate including a first laminate provided on the substrate and laminated with a plurality of first elect...

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Bibliographic Details
Main Author UCHIYAMA YASUHIRO
Format Patent
LanguageEnglish
Japanese
Published 26.09.2019
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Summary:To provide a semiconductor storage device capable of improving product performance and reliability.SOLUTION: A semiconductor storage device according to an embodiment comprises: a substrate; a laminate including a first laminate provided on the substrate and laminated with a plurality of first electrode layers and a second laminate provided on the first laminate and including at least one second electrode layer; a hole penetrating the first laminate and the second laminate in a first direction perpendicular to the substrate and including a first insulator; and a channel film located between the first insulator and the first electrode layer and between the first insulator and the second electrode layer and including a first portion and a second portion facing each other across the first insulator. A first memory part located between the first electrode layer and the first portion is electrically insulated from a second memory part located between the first electrode layer and the second portion. A third memory part located between the second electrode layer and the first portion is electrically connected to a fourth memory part located between the second electrode layer and the second portion.SELECTED DRAWING: Figure 2 【課題】製品性能および信頼性を改善することが可能な半導体記憶装置を提供する。【解決手段】実施形態に係る半導体記憶装置は、基板と、基板上に設けられ、複数の第1電極層が積層された第1積層体と、第1積層体上に設けられ少なくとも1層の第2電極層を含む第2積層体と、を有する積層体と、第1積層体および第2積層体を基板に垂直な第1方向に貫通し、第1絶縁体 を有するホールと、第1絶縁体と第1電極層との間、および第1絶縁体と第2電極層との間に位置し、第1絶縁体を挟んで互いに対向する第1部分および第2部分を有するチャネル膜と、を備える。第1電極層と第1部分との間に位置する第1メモリ部と、第1電極層と第2部分との間に位置する第2メモリ部は電気的に絶縁され、第2電極層と第1部分との間に位置する第3メモリ部と、第2電極層と第2部分との間に位置する第4メモリ部は電気的に接続されている。【選択図】図2
Bibliography:Application Number: JP20180052841