SEMICONDUCTOR DEVICE

To downsize a semiconductor device.SOLUTION: A semiconductor device SD comprises a semiconductor chip CHa including an inductor element L1 and an inductor element L2 on a principal surface PSa side, a semiconductor chip CHb including an inductor element L3 on a principal side PSb side, and a semicon...

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Bibliographic Details
Main Authors NAKASHIBA YASUTAKA, IIDA TETSUYA, KUWABARA SHINICHI
Format Patent
LanguageEnglish
Japanese
Published 12.09.2019
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Summary:To downsize a semiconductor device.SOLUTION: A semiconductor device SD comprises a semiconductor chip CHa including an inductor element L1 and an inductor element L2 on a principal surface PSa side, a semiconductor chip CHb including an inductor element L3 on a principal side PSb side, and a semiconductor chip CHc including an inductor element L4 on a principal surface PSc side. The inductor element L1 and the inductor element L2 are arranged separated from each other in a first direction Y of a principal surface PSa. The principal surface Psa faces the principal surface PSb, and the inductor element L1 and the inductor element L3 overlap with each other. Furthermore, the principal surface PSa faces the principal surface PSc, and the inductor element L2 and the inductor element L4 overlap with each other. A creepage distance CD1 between the semiconductor chip CHb and the semiconductor chip CHc is greater than a clearance Dbc between the semiconductor chip CHb and the semiconductor chip CHc.SELECTED DRAWING: Figure 10 【課題】半導体装置を小型化する。【解決手段】半導体装置SDは、主面PSa側にインダクタ素子L1およびインダクタ素子L2を有する半導体チップCHaと、主面PSb側にインダクタ素子L3を有する半導体チップCHbと、主面PSc側にインダクタ素子L4を有する半導体チップCHcと、を有する。そして、インダクタ素子L1とインダクタ素子L2とは、主面PSaの第1方向Yにおいて互いに離間して配置されており、主面PSaと主面PSbとは対向し、インダクタ素子L1とインダクタ素子L3とは互いに重なっている。さらに、主面PSaと主面PScとは対向し、インダクタ素子L2とインダクタ素子L4とは互いに重なっており、半導体チップCHbと半導体チップCHcとの間の沿面距離CD1は、半導体チップCHbと半導体チップCHcとの間の離間距離Dbcよりも大きい。【選択図】図10
Bibliography:Application Number: JP20180037573