SEMICONDUCTOR DEVICE AND EQUIPMENT
To suppress variations in an output signal of an amplification transistor.SOLUTION: The semiconductor device includes: a first semiconductor region of a first conductivity type in which potential to be detected appears; a second semiconductor region of a second conductivity type that forms a PN junc...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
25.07.2019
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Subjects | |
Online Access | Get full text |
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Summary: | To suppress variations in an output signal of an amplification transistor.SOLUTION: The semiconductor device includes: a first semiconductor region of a first conductivity type in which potential to be detected appears; a second semiconductor region of a second conductivity type that forms a PN junction with the first semiconductor region; an amplification transistor having a gate connected to the first semiconductor region; and a reset transistor for resetting potential of the first semiconductor region. One of a source and a drain of the reset transistor is connected to the first semiconductor region. The other of the source and the drain of the reset transistor is connected to the second semiconductor region.SELECTED DRAWING: Figure 2
【課題】 増幅トランジスタの出力信号のばらつきを抑制する。【解決手段】 検出する電位が現れる第1導電型の第1半導体領域と、第1半導体領域とPN接合を成す第2導電型の第2半導体領域と、第1半導体領域が接続されたゲートを有する増幅トランジスタと、第1半導体領域の電位をリセットするリセットトランジスタと、を備え、リセットトランジスタのソースおよびドレインの一方は第1半導体領域に接続され、リセットトランジスタのソースおよびドレインの他方は第2半導体領域に接続されている。【選択図】 図2 |
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Bibliography: | Application Number: JP20180004913 |