POWER SEMICONDUCTOR DEVICE

• Main Authors: TANIGUCHI KATSUMI, HORI MOTOHITO
• Format: Patent
• Language: English; Japanese
• Published: 13.06.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a power semiconductor device that is small in size and that has low inductance, and that can reduce fluctuation in resistance value of a control resistor caused by heat generation of a semiconductor element.SOLUTION: A power semiconductor device comprises: a first conductive pattern layer 11_1; semiconductor elements Q1-Q6 individually bonded on an upper surface of the first conductive pattern layer 11_1; a second conductive pattern layer 11_2a separated from the first conductive pattern layer 11_1; a control terminal 53 bonded with the second conductive pattern layer 11_2a; a control resistor 20 bonded on an upper surface of the second conductive pattern layer 11_2a; a control resistor pin 21 bonded on an upper surface of the control resistor 20; and a wiring board 4 that has a control wiring pattern layer 41 for electrically connecting among the semiconductor elements Q1-Q6 and the control resistor pin 21.SELECTED DRAWING: Figure 4 【課題】小型且つ低インダクタンスであり、半導体素子の発熱に起因する制御抵抗の抵抗値の変動を低減可能な電力用半導体装置を提供する。【解決手段】第１導電性パターン層１１_1と、第１導電性パターン層１１_1の上面にそれぞれ接合された半導体素子Ｑ１〜Ｑ６と、第１導電性パターン層１１_1と離間した第２導電性パターン層１１_2ａと、第２導電性パターン層１１_2ａに接合された制御端子５３と、第２導電性パターン層１１_2ａの上面に接合された制御抵抗２０と、制御抵抗２０の上面に接合された制御抵抗ピン２１と、半導体素子Ｑ１〜Ｑ６と制御抵抗ピン２１との間を電気的に接続する制御配線パターン層４１を有する配線基板４とを備える。【選択図】図４