SEMICONDUCTOR CHIP

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device is characterized in that sloped portions SLP are formed on connection parts between a pad PD and a lead-out wiring portion DWU. This can suppress crack formation in a coating area where a part of the pad PD is covered...

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Bibliographic Details
Main Authors TOMITA KAZURO, TAKEWAKA HIROKI
Format Patent
LanguageEnglish
Japanese
Published 18.04.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:To improve reliability of a semiconductor device.SOLUTION: A semiconductor device is characterized in that sloped portions SLP are formed on connection parts between a pad PD and a lead-out wiring portion DWU. This can suppress crack formation in a coating area where a part of the pad PD is covered with a surface protective film PAS.SELECTED DRAWING: Figure 6 【課題】半導体装置の信頼性を向上する。【解決手段】実施の形態における特徴点は、パッドＰＤと引き出し配線部ＤＷＵとの接続部位に傾斜部ＳＬＰを設けている点にある。これにより、パッドＰＤの一部を表面保護膜ＰＡＳによって被覆する被覆領域にクラックが発生することを抑制することができる。【選択図】図６
Bibliography:Application Number: JP20190012206