WIRING BOARD AND MANUFACTURING METHOD THEREOF

To provide a wiring board and a manufacturing method thereof capable of arranging grooves of fine width with less number of steps while enabling high frequency correspondence of the wiring board by a shielding structure.SOLUTION: There is provided a wiring board including an inner layer wiring havin...

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Bibliographic Details
Main Authors KODAIRA MASAYUKI, HATAZAWA HIROKI, ISODA SATOSHI, TAMURA TADASHI
Format Patent
LanguageEnglish
Japanese
Published 21.02.2019
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Summary:To provide a wiring board and a manufacturing method thereof capable of arranging grooves of fine width with less number of steps while enabling high frequency correspondence of the wiring board by a shielding structure.SOLUTION: There is provided a wiring board including an inner layer wiring having a signal wiring and an inner layer land, insulating layers disposed above and below the inner layer wiring, a ground wiring disposed in an upper layer and a lower layer via the upper and lower insulating layers, and a groove disposed around the signal wiring and the inner layer land and formed through the insulating layer from the ground wiring and a groove inner conductor disposed in the groove, and the ground wiring includes a first conductor layer directly disposed on the insulating layer and a linear opening formed in the first conductor layer, and the first conductor layer has an eave portion protruding into the width of the groove at an end portion on the linear opening side, and the groove inner conductor is connected to the first conductor layer at the eave portion, and there is provided a manufacturing method of the wiring board.SELECTED DRAWING: Figure 2 【課題】シールド構造による配線基板の高周波対応を可能としつつ、従来よりも微細な幅の溝を少ない工数で配置することが可能な配線基板及びその製造方法を提供する。【解決手段】信号配線及び内層ランドを有する内層配線と、この上下に配置される絶縁層と、この上下の絶縁層を介して、上層及び下層に配置されたグランド配線と、前記信号配線及び内層ランドの周囲に配置され、前記グランド配線から、前記絶縁層を貫通して形成された溝及びこの溝内に配置された溝内導体と、を備える配線基板であって、前記グランド配線が、前記絶縁層上に直接配置された第1の導体層と、この第1の導体層に形成された線状の開口と、を有し、前記第1の導体層が、前記線状の開口側の端部において、前記溝の幅内に飛び出した庇部を有し、前記溝内導体が、前記庇部において前記第1の導体層と接続される、配線基板及びその製造方法。【選択図】図2
Bibliography:Application Number: JP20170150708