RADIO RECEPTION CIRCUIT

To improve reception performance of a radio reception circuit by improving accuracy of AD conversion.SOLUTION: A radio reception circuit demodulates a reception signal received via an antenna 30. The radio reception circuit includes: a clock signal generator 11 for generating a clock signal; a refer...

Full description

Saved in:
Bibliographic Details
Main Author MORISAKA SHINICHI
Format Patent
LanguageEnglish
Japanese
Published 17.01.2019
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:To improve reception performance of a radio reception circuit by improving accuracy of AD conversion.SOLUTION: A radio reception circuit demodulates a reception signal received via an antenna 30. The radio reception circuit includes: a clock signal generator 11 for generating a clock signal; a reference signal generator 12 for generating a reference signal with higher frequency accuracy than the clock signal generator; a first ADC 13 for performing AD conversion of the reception signal according to the clock signal; a second ADC 14 for performing AD conversion of the reference signal according to the clock signal; a frequency error detector 22 for detecting a frequency error of the clock signal based on an apparent period difference of the reference signal identified with an output signal of the second ADC against a nominal period of the reference signal generator; a correction signal generator 24 for generating a digital signal for correction which represents a waveform oscillating at a correction frequency according to a detected frequency error of the clock signal; and a multiplier 21 for multiplying the digital signal for correction by the output signal of the first ADC.SELECTED DRAWING: Figure 1 【課題】AD変換の精度を向上することで無線受信回路の受信性能を向上する。【解決手段】無線受信回路は、アンテナ30を介して受信された受信信号を復調する。無線受信回路は、クロック信号を発生するクロック信号発生部11と、クロック信号発生部よりも高い周波数精度で参照信号を発生する参照信号発生部12と、クロック信号に従って受信信号をAD変換する第1ADC13と、クロック信号に従って参照信号をAD変換する第2ADC14と、参照信号発生部の公称周期に対する、第2ADCの出力信号から特定される参照信号の見かけ上の周期のずれに基づいてクロック信号の周波数誤差を検出する周波数誤差検出部22と、検出されたクロック信号の周波数誤差に応じた補正周波数で振動する波形を表す補正用デジタル信号を発生する補正信号発生部24と、補正用デジタル信号を第1ADCの出力信号に乗算する乗算部21とを具備する。【選択図】図1
Bibliography:Application Number: JP20170120904